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US 8,040,953 B2Granted
Reliability metric generation for trellis-based detection and/or decoding
AssigneeMarvell World Trade Ltd.
InventorsShaohua Yang, Seo-How Low, Zining Wu, Gregory Burd
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Abstract
The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology computes soft reliability information for each detected/decoded bit or codeword syndrome value.
Claims18
A method for generating reliability metrics for decoded bits, the method comprising:
- receiving a plurality of error event patterns associated with the decoded bits and a plurality of error event reliability metrics associated with the respective plurality of error event patterns, wherein each of the plurality error event patterns includes at least two bits;
- selecting a bit location for one of the decoded bits;
- determining which of the plurality of error event patterns indicates an error in the selected bit location regardless of errors in other bit locations;
- for each of the determined plurality of error event patterns, providing a bit-error likelihood value indicating the likelihood of an error in the selected bit location exclusively of the other bit locations based at least in part on the error event reliability metrics associated with the respective error event patterns;
- and
- determining, as a bit-error reliability metric for the selected bit location, the smallest bit-error likelihood value provided for the selected bit location from all of the bit-error likelihood values provided for the determined plurality of error event patterns.
3 more elements
A system for generating reliability metrics for decoded bits, the system comprising:
- a receiver operable to:
- receive a plurality of error event patterns associated with the decoded bits and a plurality of error event reliability metrics associated with the respective plurality of error event patterns, wherein each of the plurality error event patterns includes at least two bits,
- select a bit location for one of the decoded bits,
- determine which of the plurality of error event patterns indicates an error in the selected bit location regardless of errors in other bit locations, and
- provide a bit-error likelihood value indicating the likelihood of an error in the selected bit location exclusively of the other bit locations, for each of the determined plurality of error event patterns based at least in part on the error event reliability metrics associated with the respective error event patterns;
- and
- an N-way minimum finder circuit that determines, as a bit-error reliability metric for the selected bit location, the smallest bit-error likelihood value provided for the selected bit location from all of the bit-error likelihood values provided for the determined plurality of error event patterns.
4 more elements
A system for generating reliability metrics for decoded bits, the system comprising:
- means for receiving a plurality of error event patterns associated with the decoded bits and a plurality of error event reliability metrics associated with the respective plurality of error event patterns, wherein each of the plurality error event patterns includes at least two bits;
- means for selecting a bit location for one of the decoded bits;
- means for determining which of the plurality of error event patterns indicates an error in the selected bit location regardless of errors in other bit locations;
- for each of the determined plurality of error event patterns, means for providing a bit-error likelihood value indicating the likelihood of an error in the selected bit location exclusively of the other bit locations based at least in part on the error event reliability metrics associated with the respective error event patterns;
- and
- means for determining, as a bit-error reliability metric for the selected bit location, the smallest bit-error likelihood value provided for the selected bit location from all of the bit-error likelihood values provided for the determined plurality of error event patterns.
3 more elements
Dependencies are inferred from the claim text.