Method for shape and timing equivalent dimension extraction
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYing-Chou Cheng, Chih-Ming Lai, Ru-Gun Liu, Tsong-Hua Ou, Min-Hong Wu, Yih-Yuh Doong, Hsiao-Shu Chao, Yi-Kan Cheng, Yao-Ching Ku, Cliff Hou
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Abstract
An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
Claims18
A non-transitory machine-readable storage medium having machine-executable instructions embodied thereon, the instructions for performing an integrated circuit (IC) design method comprising:
- providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data, the IC layout contour being defined by an overlap region of a gate contour and an active region contour;
- generating a maximum rectangle inside the IC layout contour;
- generating an effective rectangle layout to represent the IC layout contour, wherein the generating an effective rectangle layout includes finding a width correction and a length correction to the maximum rectangle;
- and
- simulating the IC device using the effective rectangular layout, the simulating including:
- finding a width sensitivity of the width correction to an electrical parameter of the IC device;
- and
- finding a length sensitivity of the length correction to the electrical parameter.
A non-transitory machine-readable storage medium having machine-executable instructions embodied thereon, the instructions for performing an integrated circuit (IC) design method comprising:
- providing an IC design layout of an IC device;
- simulating, with manufacturing data, a manufacturing process to generate a virtual fabricated feature corresponding to a feature of the IC design layout, the virtual fabricated feature represented by a feature contour;
- generating a maximum rectangle inside of the feature contour, the maximum rectangle being the largest rectangle that will fit inside of the feature contour;
- applying a width correction and a length correction to the maximum rectangle to generate an effective rectangle;
- simulating the electrical performance of the IC device using the effective rectangle, the simulating including:
- finding a width sensitivity of the width correction to an electrical parameter of the IC device;
- and
- finding a length sensitivity of the length correction to the electrical parameter.
Dependencies are inferred from the claim text.