Through wafer via and method of making same
AssigneeInternational Business Machines Corporation
InventorsHanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
Life of this patent
Estimating the term…
Abstract
A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure.
Claims30
A structure, comprising:
- a semiconductor substrate having a top surface and an opposite bottom surface;
- an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of said array of through wafer vias independently extending from said top surface of said substrate to between greater than halfway to and all the way to said bottom surface of said substrate, said at least one electrically conductive through wafer via electrically isolated from all of said semiconductor substrate;
- and
- wherein there is no independent island of semiconductor substrate material between said at least one electrically conductive through wafer via and said semiconductor substrate.
A method, comprising:
- forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of said array of through wafer vias independently extending from said top surface of said substrate to between greater than halfway to and all the way to said bottom surface of said substrate, said at least one electrically conductive through wafer via electrically isolated from all of said semiconductor substrate;
- and
- wherein there is no independent island of semiconductor substrate material between said at least one electrically conductive through wafer via and said semiconductor substrate.
A method, comprising:
- (a) forming a first trench and a second trench in a semiconductor substrate, said first and second trenches independently extending from a top surface of said substrate toward an opposite bottom surface of said substrate a distance less than a thickness of said substrate;
- (b) simultaneously completely filling said first trench with a dielectric material and forming a liner of said dielectric material on sidewalls of said second trench;
- (c) filling remaining space in said second trench with an electrically conductive material, and
- (d) thinning said substrate from said bottom surface of said substrate to form a new bottom surface of said substrate, said dielectric material of said first trench and said liner and electrically conductive material of said second trench exposed in said new bottom surface of substrate, wherein there is no independent island of semiconductor substrate material between said electrically conductive material of said second trench and said liner of said dielectric material of said seconds trench.
A signal transmission line through a semiconductor substrate, said substrate having a top surface and an opposite bottom surface, comprising:
- a conductive through via extending from said top surface of said substrate to said bottom surface of said substrate, sidewalls of said conductive through via electrically insulated from all of said substrate, wherein there is no independent island of semiconductor substrate material between said at least one electrically conductive through wafer via and said semiconductor substrate;
- and
- a non-conductive through via extending greater than halfway or all the way from said top surface to said bottom surface of said substrate, said nonconductive through via proximate to and separated from said conductive through wafer by a region of said substrate.
Dependencies are inferred from the claim text.