Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch

An integrated circuit device, comprising:

• a substrate region that forms part of a substrate of the integrated circuit device, the substrate region including a number of diffusion regions of transistors;
• and
• a gate electrode level region that forms part of a gate electrode level of the integrated circuit device, the gate electrode level region formed over the substrate region, the gate electrode level region including a plurality of linear conductive segments each formed to have a respective length and a respective width when viewed from above, wherein the plurality of linear conductive segments are formed to have their lengths extend in a first direction in a parallel manner, and
• wherein the plurality of linear conductive segments includes linear conductive segments that form gate electrodes of four transistors of a first transistor type and gate electrodes of four transistors of a second transistor type, and
• wherein a gate electrode of a first transistor of the first transistor type is electrically connected to a gate electrode of a first transistor of the second transistor type by a first linear-shaped conductive segment within the gate electrode level region, and
• wherein a gate electrode of a second transistor of the first transistor type is electrically connected to a gate electrode of a second transistor of the second transistor type by a second linear-shaped conductive segment within the gate electrode level region, and
• wherein both a gate electrode of a third transistor of the first transistor type and a gate electrode of a fourth transistor of the first transistor type are collectively positioned between the gate electrode of the first transistor of the first transistor type and the gate electrode of the second transistor of the first transistor type, and
• wherein the gate electrodes of the first, second, third, and fourth transistors of the first transistor type are positioned in a side-by-side manner according to a substantially equal centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction, and
• wherein both a gate electrode of a third transistor of the second transistor type and a gate electrode of a fourth transistor of the second transistor type are collectively positioned between the gate electrode of the first transistor of the second transistor type and the gate electrode of the second transistor of the second transistor type, and
• wherein the gate electrodes of the first, second, third, and fourth transistors of the second transistor type are positioned in a side-by-side manner according to the substantially equal centerline-to-centerline spacing as measured in the second direction perpendicular to the first direction.