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US 8,030,697 B2Granted
Cell structure of semiconductor device having an active region with a concave portion
AssigneeSamsung Electronics Co., Ltd.
InventorsMin-Hee Cho, Seung-Bae Park
Life of this patent
Estimating the term…
Abstract
A cell structure of a semiconductor device includes an active region, having a concave portion, and an inactive region that defines the active region. A gate pattern in the active region is arranged perpendicular to the active region. A landing pad on the active region and the inactive region contacts the active region. A bit line pattern on the inactive region intersects the gate pattern perpendicularly, the bit line pattern being electrically connected to the landing pad and having a first protrusion corresponding to the concave portion of the active region.
Claims11
A cell structure of a semiconductor device, comprising:
- a first active region in a semiconductor substrate, the first active region having a first concave portion;
- an inactive region in the semiconductor substrate defining the first active region;
- a first gate pattern in the first active region, the first gate pattern being arranged perpendicular to the first active region;
- a first landing pad on the first active region and the inactive region contacting the first active region;
- and
- a bit line pattern on the inactive region configured to intersect the first gate pattern perpendicularly, the bit line pattern being electrically connected to the first landing pad,
- wherein the bit line pattern comprises a first protrusion extending over the first active region opposite the first concave portion of the first active region and a second protrusion extending into a second concave portion of a second active region adjacent the first active region.
4 more elements
A cell structure of a semiconductor device, comprising:
- a first active region in a semiconductor substrate, the first active region having a first concave portion;
- a second active region in the semiconductor substrate, the second active region having a second concave portion;
- an inactive region in the semiconductor substrate defining the first and second active regions;
- a first gate pattern in the first active region, the first gate pattern being arranged perpendicular to the first active region;
- a second gate pattern in the second active region, the second gate pattern being arranged perpendicular to the second active region;
- a first landing pad on the first active region and the inactive region contacting the first active region;
- a bit line pattern on the inactive region configured to intersect the first and second gate patterns perpendicularly, the bit line pattern being electrically connected to the first landing pad, wherein the bit line pattern has a first protrusion extending from a first lateral portion of the bit line pattern to overlap a lateral portion of the first active region, which is located opposite to the first concave portion of the first active region, and has a second protrusion extending from a second lateral portion of the bit line pattern into the second concave portion of the second active region;
- and
- a bit line contact between the first landing pad and the bit line pattern, the bit line contact contacting the first landing pad and the bit line pattern on the first inactive region,
- wherein the first concave portion of the first active region is in a selected lateral portion of the first active region, which overlaps a portion of the first gate pattern, and
- wherein the first and second gate patterns are parallel to each other and extend across the first and second concave portions, and the first and second protrusions of the bit line pattern.
8 more elements
A cell structure of a semiconductor device, comprising:
- a first active region in a semiconductor substrate, the first active region having a first concave portion;
- a second active region in the semiconductor substrate, the second active region having a second concave portion;
- an inactive region in the semiconductor substrate defining the first and second active regions;
- a first gate pattern arranged across the first and second active regions;
- a first landing pad on the first active region and the inactive region contacting the first active region;
- and
- a bit line pattern on the inactive region configured to intersect the first gate pattern perpendicularly, the bit line pattern being electrically connected to the first landing pad and having a protrusion extending into the second concave portion of the second active region.
4 more elements
Dependencies are inferred from the claim text.