Providing extended memory protection
AssigneeIntel Corporation
InventorsAntonio S. Cheng, Francis X. McKeen
Life of this patent
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Abstract
In one embodiment, the present invention provides for extended memory protection for memory of a system. The embodiment includes a method for associating a protection indicator of a protection record maintained outside of an application's data space with a memory location, and preventing access to the memory location based on the status of the protection indicator. In such manner, more secure operation is provided, as malicious code or other malware is prevented from accessing protected memory locations. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a processor including a first memory to store copies of protection vectors, wherein the protection vectors include a plurality of indicators each to identify a protection status of an addressable element of a system memory, and a first buffer coupled to the first memory, the first buffer to store entries each including a first translation to a physical address for an addressable element of the system memory and a second translation to a physical address for the protection vector stored in the system memory associated with the addressable element;
- and
- the system memory coupled to the processor.
A processor comprising:
- a first memory to store copies of protection vectors stored in a first portion of a system memory, wherein each of the protection vectors includes a plurality of bits, each to identify a protection status of an addressable memory element of a data page of the system memory, wherein the first portion of the system memory is inaccessible in a virtual address space of a program.
A system comprising:
- a processor including a plurality of processor cores each including a protection cache to store copies of protection vectors stored in a first portion of a system memory, each of the protection vectors including a plurality of bits to identify a protection status of an addressable memory element of a data page of the system memory, and a protection translation lookaside buffer (TLB) coupled to the protection cache to store translations each between a virtual address and a corresponding physical address of a protection vector stored in the first system memory portion, the protection TLB to generate a hit signal and to provide the hit signal to the protection cache, the protection cache and the protection TLB separate from a page translation mechanism of the processor;
- and
- the system memory coupled to the processor, wherein the system memory comprises a dynamic random access memory (DRAM).
Dependencies are inferred from the claim text.