Automated method and apparatus for very early validation of chip power distribution networks in semiconductor chip designs
AssigneeInternational Business Machines Corporation
InventorDieu Q. Phan Vogel
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Abstract
Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid design data. Common power connection and distribution errors are automatically addressed as an integral part of the early chip floor planning and chip power build processes providing efficient solutions requiring no extra wiring resource to be implemented and reducing the runtime of required final full-chip physical design checks, and the overall design cycle.
Claims20
An automated method of generating a semiconductor chip layout including validating a chip-level physical power distribution network to produce a corrected chip power grid, comprising:
- performing, by a computer, a plurality of checks dispersed through a final chip design process for detecting and correcting power connection problems as an integral part of a chip designing process by:
- using coded connectivity attributes in a chip power grid and a chip floor plan for a chip design to speed up a checking process;
- analyzing a full-chip power distribution network against circuit abstracts in the chip floor plan in place of actual circuit layouts for chips;
- and
- checking each power metal level in the network in succession against a power level above and/or below without building a complete logical representation of chip power metallurgy and via structure.
A computer program product having a program embodied on a non-transitory computer useable medium which, when executed by a computer, causes the computer to implement an automated method for validating a chip-level physical power distribution network for a semiconductor chip to produce a corrected chip power grid by detecting and correcting power connection problems during a chip design process and as an integral part of a chip power routing process, comprising:
- code for using coded connectivity attributes in a chip power grid and a chip floor plan for a chip design to speed up a checking process;
- code for analyzing a full-chip power distribution network against a chip floor plan containing circuit abstracts in place of actual circuit layouts;
- and
- code for checking each power metal level in succession against a power level above and/or below without building a complete logical representation of chip power metallurgy and via structure.
Dependencies are inferred from the claim text.