Parallel scan paths with header data circuitry and header return circuitry
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
Claims9
An integrated circuit comprising:
- A. logic circuitry;
- B. parallel scan paths coupled to the logic circuitry, each scan path having a scan input and a scan output;
- C. stimulus data circuitry having a serial input, control inputs, a serial output, and parallel outputs coupled with the scan inputs of the parallel scan paths;
- D. header data circuitry having a serial input connected with the serial output of the stimulus data circuitry, control inputs, and a command output;
- E. response data circuitry having parallel inputs coupled with the scan outputs, control inputs, a serial input, and a serial output;
- F. header return circuitry having an input connected with the command output of the header data circuitry, control inputs, and a serial output connected with the serial input of the response data circuitry;
- and
- G. controller circuitry having control outputs connected with the control inputs of the scan paths, the stimulus data circuitry, the header data circuitry, the response data circuitry, and the header return circuitry, a clock input, and a command input connected with the command output of the header data circuitry.
Dependencies are inferred from the claim text.