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US 8,028,206 B2Granted
Memory device including memory controller
AssigneeKabushiki Kaisha Toshiba
InventorHiroshi Sukegawa
Life of this patent
Estimating the term…
Abstract
A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.
Claims20
A memory device comprising:
- a semiconductor memory including a plurality of memory cells;
- and
- a memory controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and a data correction circuit which corrects a value of data at an address corresponding to the predetermined data pattern, in accordance with a result of the check, and sends the corrected value to the semiconductor memory.
A memory device comprising:
- a semiconductor memory including a plurality of memory cells;
- and
- a memory controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and a data correction circuit which shifts a level of a value of data at an address corresponding to the predetermined data pattern, in accordance with a result of the check, and sends the level-shifted value to the semiconductor memory.
Dependencies are inferred from the claim text.