Protocol for transitioning in and out of zero-power state

A method comprising:

• recognizing and trapping a command that comprises a request to transition one or more sections of a processing unit to a power-saving state;
• in response to said recognizing the command, notifying a control circuit of the processing unit of the request;
• the control circuit of the processing unit determining, based on the request, that the power-saving state is a zero-power state;
• the control circuit of the processing unit asserting a first interrupt signal in response to said determining;
• and
• performing a sequence of steps that result in the one or more sections of the processing unit transitioning to the zero-power state in response to said asserting the first interrupt signal.

A processor comprising:

• a core operating according to a power supply voltage and a clock signal, and operable to execute a first microcode;
• and
• a controller interfacing with the core;
• wherein the first microcode is executable to recognize and trap a first command requesting a low-power state for the core, wherein the first microcode is further executable to request the controller to transition the core to the low-power state in response to having recognized the first command;
• wherein in response to being requested to transition the core to the low-power state, the controller is operable to determine whether the low-power state is a zero-power state;
• wherein the controller is operable to initiate a transition of the core to the zero-power state, in response to the control circuit having determined that the low-power state is the zero-power state;
• wherein the first microcode is executable to complete one or more tasks required prior to placing the core in the zero-power state, in response to the controller having initiated the transition of the core to the zero-power state;
• wherein the first microcode is executable to instruct the controller of the one or more tasks having been completed;
• and
• wherein in response to being instructed of the one or more tasks having been completed, the controller is operable to issue respective requests to lower the power supply voltage to a zero-power voltage level and uncouple the clock signal from the core.

A system operable to run an operating system (OS), the system comprising:

• a processor configured to operate according to a power supply voltage and a clock;
• and
• system memory interfacing with the processor;
• wherein the processor is operable to recognize and trap a first instruction, issued by the OS or a program running under the OS, for transitioning at least one section of the processor to a low-power state;
• wherein in response to recognizing the first instruction, the processor is operable to determine whether the low-power state is a zero-power state based on the first instruction, and assert an interrupt signal if the processor has determined that the low-power state is a zero-power state;
• and
• wherein in response to the processor having asserted the interrupt signal, the processor is operable to store processor data in the system memory or in processor memory external to the at least one section of the processor, wherein the processor data corresponds to a current state of the at least one section of the processor;
• wherein in response to the processor having stored the processor data, the processor is operable to issue respective requests to lower the power supply voltage to a zero-power voltage level for the at least first section of the processor, and uncouple the clock from the at least first section of the processor.

A processor comprising:

• one or more processor cores, each respective processor core of the one or more processor cores comprising:
• one or more state registers;
• and
• non-volatile memory configured to store microcode instructions executed by the respective processor core;
• a power management controller interfacing with the non-volatile memory of each respective processor core of the one or more processor cores;
• and
• a state monitor interfacing with the power management controller;
• wherein the power management controller is configured to communicate with the non-volatile memory of each respective processor core of the one or more processor cores to recognize when a request is made to transition the respective processor core of the one or more processor cores to a low-power state;
• and
• wherein the power management controller is configured to communicate with the state monitor to determine whether to transition the respective processor core of the one or more processor cores to a zero-power state if the request to transition the respective processor core of the one or more processor cores to a low-power state is a request to transition the respective processor core of the one or more processor cores to a zero-power state.