Processor power consumption control and voltage drop via micro-architectural bandwidth throttling
AssigneeIntel Corporation
InventorsSanjeev Jahagirdar, Edward Gamsaragan, Scott E. Siers
Life of this patent
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Abstract
A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
Claims25
A method, comprising:
- supplying a processor with a first voltage, the first voltage being below a second voltage, the second voltage being the lowest compatible voltage for an enhanced processor halt state;
- allowing the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
A device, comprising:
- processor power management circuitry to:
- supply a processor with a first voltage, the first voltage being below a second voltage, the second voltage being the lowest compatible voltage for an enhanced processor halt state;
- allow the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
A system, comprising:
- a multi-core processor;
- a voltage regulator;
- and
- processor power management circuitry to:
- cause the voltage regulator to supply the processor with a first voltage, the first voltage being below a second voltage, the second voltage being the lowest compatible voltage for an enhanced processor halt state;
- allow the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
Dependencies are inferred from the claim text.