Data dependent instruction decode
AssigneeInternational Business Machines Corporation
InventorsMark J Hickey, Adam J Muff, Matthew R Tubbs, Charles D Wait
Life of this patent
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Abstract
A circuit arrangement and method support data dependent instruction decoding, whereby instructions are decoded, in part, using decode data that is stored in operand registers identified by such instructions. An instruction may include an opcode and at least one operand that identifies a register. During execution of the instruction, the instruction is first decoded using the opcode, and then decode data stored in the operand register is retrieved and used to further decode the instruction, e.g., to select from among a plurality of operations or instruction types associated with the same opcode.
Claims25
A method of executing floating point instructions from an instruction set, wherein the instruction set defines a plurality of floating point instruction types respectively associated with a plurality of opcodes, wherein a first opcode among the plurality of opcodes is associated with a plurality of floating point operations, and wherein each floating point operation among the plurality of floating point operations is associated with a decode value among a plurality of decode values, the method comprising, in response to receiving a first floating point instruction:
- performing a primary decode of the first floating point instruction based upon an opcode associated therewith;
- and
- in response to determining that the opcode associated with the first floating point instruction matches the first opcode:
- retrieving a first floating point register identified by the first instruction from a floating point register file, wherein the first floating point register stores an exponent in an exponent portion thereof, a significand in a most significant subset of a significand portion thereof and a decode value in a least significant subset of the significand portion thereof;
- after retrieving the first floating point register, performing a supplemental decode of the first floating point instruction using the decode value stored in the first floating point register to identify a first floating point operation from among the plurality of floating point operations that is associated with the decode value stored in the first floating point register;
- and
- after performing the supplemental decode of the first floating point instruction, executing the first floating point instruction in a floating point execution unit by performing the first floating point operation using the exponent and significand stored in the first floating point register.
A circuit arrangement, comprising:
- a register file including a plurality of registers, the plurality of registers including a first register, the first register storing operand data in an operand portion thereof and decode data in a decode portion thereof;
- execution logic coupled to the register file and configured to execute a first instruction that identifies the first register in the register file, wherein the execution logic is further configured to use the operand data stored in the operand portion of the first register as input data during execution of the first instruction;
- and
- decode logic coupled to the execution logic and configured to use the decode data stored in the decode portion of the first register identified by the first instruction to decode the first instruction.
A method of executing instructions using execution logic coupled to a register file, the method comprising:
- executing a first instruction that identifies a first register from the register file using the execution logic, wherein the first register stores operand data in an operand portion thereof and decode data in a decode portion thereof, and wherein executing the first instruction includes using the operand data stored in the operand portion of the first register as input data;
- and
- during execution of the first instruction, using the decode data stored in the decode portion of the first register identified by the first instruction to decode the first instruction.
Dependencies are inferred from the claim text.