Hierarchical multi-threading processor for executing virtual threads in a time-multiplexed fashion

A method of executing instructions in a hierarchical microprocessor, the method comprising:

• obtaining the instructions for execution using a plurality of second-level instructions pipeline elements;
• storing first operand status information in the plurality of second-level instruction pipeline elements;
• dispatching, based on the first operand status information, the instructions to a plurality of first-level instruction pipeline elements included in respective execution clusters of the microprocessor;
• storing second operand status information for the instructions in the plurality of first-level instruction pipeline elements;
• dispatching, based on the second operand status information, the instructions to a plurality of respective execution units included in the execution clusters;
• executing, in the respective execution units, one or more of the instructions, wherein the instructions include multiple execution threads;
• creating one or more virtual execution threads from respective execution threads of the multiple execution threads;
• executing the virtual execution threads in a time-multiplexed fashion;
• storing age information that comprises a definition time in one or more entries of multiple store buffers, a store buffer of the multiple store buffers included in each of the plurality of first-level instruction pipeline elements, the definition time reflecting a current time at which a respective entry is written into a given first-level store buffer;
• and
• storing age information that comprises a kill time in one or more entries of the multiple store buffers, the kill time reflecting when another entry in the given first-level store buffer is subsequently written to that has a matching same address as the respective entry.

A hierarchical microprocessor comprising:

• a plurality of second-level instruction pipeline elements;
• a plurality of execution clusters, each execution cluster being operatively coupled with each of the second-level instruction pipeline elements and including:
• a plurality of first-level instruction pipeline elements, wherein each of the first-level instruction pipeline elements corresponds with a respective second-level instruction pipeline element;
• and
• one or more instruction execution units operatively coupled with each of the first-level instruction pipeline elements,
• wherein:
• the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements, the plurality of second-level instruction pipeline elements and the plurality of execution clusters;
• the microprocessor is configured to virtualize one or more of the multiple execution threads to create respective virtual threads;
• and the microprocessor is configured to execute the virtual threads in a time-multiplexed fashion;
• the second-level instruction pipeline elements and the first-level instruction pipeline elements each include:
• an instruction scheduler;
• a store buffer;
• and
• a register file structure;
• and
• the first-level store buffer of each of the first-level instruction pipeline elements includes one or more entries that are capable of storing age information that comprises at least one of a definition time or a kill time;
• and
• the microprocessor is further configured to store a definition time reflecting a current time at which a respective entry is written into a given first-level store buffer and to store a kill time that reflects when another entry in the given first-level store buffer is subsequently written to that has a matching same address as the respective entry.

A method of executing instructions in a hierarchical microprocessor, the method comprising:

• obtaining the instructions for execution using a plurality of second-level instructions pipeline elements, the instructions including multiple execution threads;
• storing first operand status information in the plurality of second-level instruction pipeline elements;
• dynamically assigning execution threads to respective execution clusters;
• dispatching, based on the first operand status information, the instructions to a plurality of first-level instruction pipeline elements included in respective execution clusters of the microprocessor;
• storing second operand status information for the instructions in the plurality of first-level instruction pipeline elements;
• dispatching, based on the second operand status information, the instructions to a plurality of respective execution units included in the execution clusters;
• executing, in the respective execution units, one or more of the instructions,
• moving execution of at least one execution thread from a first execution cluster to a second execution cluster;
• creating one or more virtual execution threads from respective execution threads of the multiple execution threads;
• executing the virtual execution threads in a time-multiplexed fashion;
• storing age information that comprises a definition time in one or more entries of multiple store buffers, a store buffer of the multiple store buffers included in each of the plurality of first-level instruction pipeline elements, the definition time reflecting a current time at which a respective entry is written into a given first-level store buffer;
• and
• storing age information that comprises a kill time in one or more entries of the multiple store buffers, the kill time reflecting when another entry in the given first-level store buffer is subsequently written to that has a matching same address as the respective entry.