Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines

A system, comprising:

• a processor,
• a memory unit;
• an input mechanism;
• an output mechanism;
• a bus coupling said processor to said memory unit, said input mechanism and said output mechanism, wherein said processor comprises:
• a fetch unit configured to retrieve instructions;
• a dispatch unit coupled to said fetched unit, wherein said dispatch unit is configured to decode said retrieved instructions;
• a plurality of instruction queues coupled to said dispatch unit, wherein said plurality of instruction queues are configured to dispatch said decoded instructions to an execution unit;
• and
• a plurality of execution units coupled to said plurality of instruction queues, wherein said plurality of execution units are configured to execute said dispatched decoded instructions;
• wherein a first of said plurality of execution units contains logic to perform:
• detecting an exception at or before a completion point for its execution pipeline, wherein said execution pipeline of said first of said plurality of execution units comprises a backup pipeline and a regular pipeline, wherein said backup pipeline stores a copy of decoded instructions issued to said regular pipeline from said plurality of instruction queues;
• asserting an upper stall point to prevent instructions from entering said backup pipeline and said regular pipeline;
• asserting a lower stall point to prevent instructions from flowing out of said backup pipeline;
• flushing instructions younger than an instruction causing said exception in said regular pipeline;
• and
• allowing instructions to flow from said backup pipeline to said regular pipeline.

A processor, comprising:

• a fetch unit configured to retrieve instructions;
• a dispatch unit coupled to said fetched unit, wherein said dispatch unit is configured to decode said retrieved instructions;
• a plurality of instruction queues coupled to said dispatch unit, wherein said plurality of instruction queues are configured to dispatch said decoded instructions to an execution unit;
• and
• a plurality of execution units coupled to said plurality of instruction queues, wherein said plurality of execution units are configured to execute said dispatched decoded instructions;
• wherein a first of said plurality of execution units contains logic to perform:
• detecting an exception at or before a completion point for its execution pipeline, wherein said execution pipeline of said first of said plurality of execution units comprises a backup pipeline and a regular pipeline, wherein said backup pipeline stores a copy of decoded instructions issued to said regular pipeline from said plurality of instruction queues;
• asserting an upper stall point to prevent instructions from entering said backup pipeline and said regular pipeline;
• asserting a lower stall point to prevent instructions from flowing out of said backup pipeline;
• flushing instructions younger than an instruction causing said exception in said regular pipeline;
• and
• allowing instructions to flow from said backup pipeline to said regular pipeline.