Memory module with reduced access granularity
AssigneeRambus Inc.
InventorsCraig E. Hampel, Frederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.
Claims31
A memory apparatus, comprising:
- a first discrete memory device;
- a second discrete memory device;
- a command bus interface;
- a data bus interface having a width with a first portion coupled to the first discrete memory device but not the second discrete memory device and a second portion coupled to the second discrete memory device but not the first discrete memory device;
- command bus interface logic, where
- in a first mode, a memory access command is interpreted as simultaneously directed to both of the first discrete memory device and the second discrete memory device to process a memory word sized to correspond to the width, and
- in a second mode, the memory access command is interpreted as directed to a selected one of the first discrete memory device or the second discrete memory device at a given instant in time to process a memory word sized to correspond to a respective one of the first portion or the second portion.
A memory apparatus, comprising:
- a first discrete memory device;
- a second discrete memory device;
- a command bus interface to provide commands to each of the first discrete memory device and the second discrete memory device;
- a data bus interface having a width with a first portion coupled to the first discrete memory device but not the second discrete memory device and a second portion coupled to the second discrete memory device but not the first discrete memory device;
- and
- circuitry to cause each of the first discrete memory device and the second discrete memory device to respond to the same command for respective portions of a data word sized to correspond to the width or to different time-staggered commands for respective data words sized to correspond to a respective one of the first portion or the second portion, in dependence on an operating mode.
A memory apparatus, comprising:
- a first memory array;
- a second memory array;
- a shared command bus interface to provide commands to each of the first memory array and the second memory array;
- a first data path for the first memory array, not shared by the second memory array, and a second data path for the second memory array, not shared by the first memory array;
- and
- means for causing the first memory array to respond to a command received via the command bus in response to a first chip select using the first data path, and means for causing the second memory array to respond to a command received via the command bus in response to a selective one of the first chip select or a second chip select using the second data path, where the first memory array and the second memory array are to process to respective portions of a data word in a first operating mode, and the first memory array and second memory array are to process respective data words in a second operating mode.
Dependencies are inferred from the claim text.