US 8,028,131 B2Granted

System and method for aggregating core-cache clusters in order to produce multi-core processors

AssigneeIntel Corporation

InventorKrishnakanth Sistla

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Abstract

According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor cores and memory.

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Claims23

Dependent claims

A processor comprising:

an on-die interconnect that enables receipt of incoming data and transmission of outgoing data;
a plurality of core-cache clusters, each of the plurality of core-cache clusters including both a cache memory and one or more processor cores in communication with the cache memory;
and
a scalability agent coupled to the on-die interconnect, the scalability agent (i) operating in accordance with a protocol to ensure that the plurality of core-cache clusters appear as a single caching agent and (ii) managing a flow of the incoming data and the outgoing data into a socket associated with at least one of the plurality of core-cache clusters.

1 more element

A processor comprising:

an on-die interconnect;
a first core-cache cluster coupled to and physically separated from the on-die interconnect, the first core-cache cluster comprises
a first plurality of processor cores,
a first memory communicatively coupled to the first plurality of processor cores, and
a first scalability agent unit in communication with the on-die interconnect, the first scalability agent unit to perform address checking operations of the first memory and to manage a flow of information via a socket associated with the first core-cache cluster;
and
a second core-cache cluster coupled to the on-die interconnect, the second core-cache cluster comprises
a second plurality of processor cores,
a second memory communicatively coupled to the second plurality of processor cores, and
a second scalability agent unit in communication with the on-die interconnect, the second scalability agent unit to perform address checking operations of the second memory and to operate with the first scalability agent unit in order to maintain local coherency of the first core-cache cluster and the second core-cache cluster so that the first core-cache cluster and the second core-cache cluster appear to operate as a single cache controller.

7 more elements

Dependencies are inferred from the claim text.

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Abstract

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Claims23

Dependent claims

A processor comprising:

an on-die interconnect that enables receipt of incoming data and transmission of outgoing data;
a plurality of core-cache clusters, each of the plurality of core-cache clusters including both a cache memory and one or more processor cores in communication with the cache memory;
and
a scalability agent coupled to the on-die interconnect, the scalability agent (i) operating in accordance with a protocol to ensure that the plurality of core-cache clusters appear as a single caching agent and (ii) managing a flow of the incoming data and the outgoing data into a socket associated with at least one of the plurality of core-cache clusters.

1 more element

A processor comprising:

an on-die interconnect;
a first core-cache cluster coupled to and physically separated from the on-die interconnect, the first core-cache cluster comprises
a first plurality of processor cores,
a first memory communicatively coupled to the first plurality of processor cores, and
a first scalability agent unit in communication with the on-die interconnect, the first scalability agent unit to perform address checking operations of the first memory and to manage a flow of information via a socket associated with the first core-cache cluster;
and
a second core-cache cluster coupled to the on-die interconnect, the second core-cache cluster comprises
a second plurality of processor cores,
a second memory communicatively coupled to the second plurality of processor cores, and
a second scalability agent unit in communication with the on-die interconnect, the second scalability agent unit to perform address checking operations of the second memory and to operate with the first scalability agent unit in order to maintain local coherency of the first core-cache cluster and the second core-cache cluster so that the first core-cache cluster and the second core-cache cluster appear to operate as a single cache controller.

7 more elements

Dependencies are inferred from the claim text.

Description4,980 words

Summary190 words

#Embodiments of the invention relate to the field of integrated circuits, and according to one embodiment of the invention, a system and method for aggregating, in a scalable manner, core-cache clusters in order to produce a variety of multi-core processors.

#Microprocessors generally include a variety of logic circuits fabricated on a single semiconductor integrated circuit (IC). These logic circuits typically include a processor core, memory, and other components. More and more high-end processors are now including more than one processor core on the same IC. For instance, multi-core processors such as Chip Multi-Processors (CMPs) for example, feature a multi-core structure that implements multiple processor cores within an IC.

#Increased silicon efficiencies are now providing new opportunities for adding additional functionality into the processor silicon. As an example, applications are taking advantage of increased multi-threading capabilities realized from an increased number of processing cores in the same processor. Hence, it is becoming important to develop a communication protocol that optimizes performance of a multi-core processor by mitigating system interconnect latency issues and ensuring that aggregated processor cores appear as one caching agent in order to avoid scalability issues and interconnect saturation.

Brief description of the drawings11 figures

#The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention.

#FIG. 1 is an exemplary block diagram of a data processing system implemented with one or more multi-core processors.

#FIG. 2 is a first exemplary block diagram of a multi-core processor with a caching bridge configuration.

Detailed description4,526 words

#Herein, certain embodiments of the invention relate to a system and scalable method for aggregating core-cache clusters of a multi-core processor. The multi-core processor interfaces with a system interconnect such as a Common System Interconnect (CSI).

#In the following description, certain terminology is used to describe features of the invention. For example, the term “core-cache cluster” is generally considered to be a modular unit that comprises one or more cores and a shared cache. Core-cache clusters are used as building blocks for a scalable, multi-core processor. For instance, several core-cache clusters may be joined together in accordance with a scalability agent protocol as described below.

#According to one embodiment of the invention, the “scalability agent protocol” is a communication scheme that enables the aggregating of core-cache clusters operating independently from each other, and provides “graceful” scalability where the responsibility for maintaining memory coherency is approximately shared equally among the core-cache clusters despite any increase or decrease in number. This is accomplished because the scalability agent protocol is partitionable among address regions in the system memory address space. The latencies to the cache in the core-cache cluster substantially remains unchanged as the number of cores increases.

Abstract

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Claims23

Abstract

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Drawings

Claims23

Description4,980 words

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Classification2 codes

Life of this patent

Description4,980 words