US 8,028,128 B2 · Method for increasing cache directory associativity classes in a system with a register space memory

Abstract

In a method of managing a cache directory in a memory system, an original system address is presented to the cache directory when corresponding associativity data is allocated to an associativity class in the cache directory. The original system address is normalized by removing address space corresponding to a memory hole, thereby generating a normalized address. The normalized address is stored in the cache directory. The normalized address is de-normalized, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for new associativity data. The de-normalized address is sent to the memory system for coherency management.

Claims15

Dependent claims

A method of managing a cache directory in a memory system, comprising the actions of:

a. presenting an original system address to the cache directory when corresponding associativity data is allocated to an associativity class in the cache directory;
b. normalizing the original system address by removing address space corresponding to a memory hole, thereby generating a normalized address;
c. storing the normalized address in the cache directory;
d. de-normalizing the normalized address, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for new associativity data;
and
e. sending the de-normalized address to the memory system for coherency management.

3 more elements

An apparatus for managing a cache directory in a memory system, comprising:

a. a memory hole size input;
b. a normalizing circuit configured to normalize an original system address by removing address space corresponding to a memory hole, thereby generating a normalized address when associativity data is allocated to a cache associativity class in a cache directory;
c. a storage circuit that is configured to store the normalized address in the cache directory;
d. a de-normalizing circuit that is configured to de-normalize the normalized address, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for a new associativity data;
and
e. a transmission circuit that is configured to send the de-normalized address to the memory system for coherency management.

3 more elements

Dependencies are inferred from the claim text.

Method for increasing cache directory associativity classes in a system with a register space memory

Life of this patent

Method for increasing cache directory associativity classes in a system with a register space memory

Life of this patent

Abstract

Claims15