System with flash memory device and data recovery method thereof

A memory system comprising:

• a nonvolatile memory device which stores block arrangement information;
• a central processing unit;
• and
• a random access memory which stores a block mapping table configured to allocate physical block addresses of the nonvolatile memory device in correspondence with logical block addresses provided from the central processing unit, the block mapping table utilizing address mapping in accordance with a wear-leveling scheme,
• wherein the central processing unit restores the block mapping table with reference to allocation block information included in the block arrangement information of the nonvolatile memory device, locates address information included in spare regions of erased blocks with reference to erased block information, and updates the block mapping table according to the located address information,
• wherein the block arrangement information is arranged in order of erase counts, and wherein blocks with the smallest erase counts are first allocated to logical block addresses provided from the central processing unit.

A system comprising:

• a central processing unit;
• a hybrid hard disk which stores data and includes a nonvolatile cache memory;
• and
• a random access memory which stores a block mapping table configured to allocate physical block addresses of the nonvolatile cache memory in correspondence with logical block addresses provided from the central processing unit, the block mapping table utilizing address mapping in accordance with a wear-leveling scheme,
• wherein the central processing unit restores the block mapping table with reference to allocation block information included in the block arrangement information of the nonvolatile cache memory, locates address information included in spare regions of erased blocks with reference to erased block information, and updates the block mapping table according to the located address information,
• wherein the block arrangement information is arranged in order of erase counts, and wherein blocks with the smallest erase counts are first allocated to logical block addresses provided from the central processing unit.