Memory module, cache system and address conversion method
AssigneeRenesas Electronics Corporation
InventorSeiji Miura
Life of this patent
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Abstract
A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips.
Claims18
A memory module comprising:
- a non-volatile memory;
- a cache memory;
- and
- a control circuit which controls accesses between said non-volatile memory and said cache memory,
- wherein the memory module is provided with a first non-volatile memory interface for accessing said cache memory from an information processing device outside of said memory module and a second non-volatile memory interface for accessing said non-volatile memory from said information processing device outside of said memory module,
- wherein data stored in the non-volatile memory is output from the second non-volatile memory interface via the cache memory when the information processing device accesses the second non-volatile memory interface,
- wherein data stored in the non-volatile memory is output from the first non-volatile memory interface without going through the cache memory when the information processing device accesses the first non-volatile memory interface, and
- wherein the first non-volatile memory interface and the second non-volatile memory interface are both connected to the information processing device, and said non-volatile memory and said cache memory are accessible at the same time independently via said first non-volatile memory interface and said second non-volatile memory interface, respectively.
Dependencies are inferred from the claim text.