Apparatus and method for serial to parallel in an I/O circuit

#1. Technical Field

#The present invention relates to an apparatus and method for an I/O circuit, in particular to an apparatus and method for serial to parallel in an I/O circuit.

#2. Description of the Prior Art

#FIG. 1 is a schematic diagram showing the output of an IC with the pin multifunction concept.

#FIG. 2A is a schematic diagram of a sequential logic circuit.

#FIG. 2B is a schematic diagram of an I/O circuit combining a plurality of sequential logic circuits.

#The present invention provides an apparatus and method for serial to parallel of an I/O circuit that enables the I/O circuit to output the input data stream quickly without latency. The description will be given with an embodiment hereinafter. However, those skilled in the art will understand that it is only an example, and is not used to limit the invention itself. The embodiment related to the present invention will be described in detail below.

#FIG. 4A shows a serial to parallel apparatus 400 of an I/O circuit according to one embodiment of the present invention, and FIG. 4B shows a detailed structural diagram of FIG. 4A. The circuit shown in FIG. 4B comprises M sequential logic circuits SL (SL0, SL1, . . . , SLM−1), while each sequential logic circuit includes a first D-type flip-flop, a second D-type flip-flop, a multiplexer, and a D-type latch. One of first D-type flip-flops D1 (D10, D11, . . . , D1M−1) receives one bit of input data, and the output of each first D-type flip-flop is directed to the input of a first D-type flip-flop of a next stage. For example, the output of the flip-flop D10 is coupled with the input of a flip-flop D11, which is the next stage of the flip-flop D10. One of second D-type flip-flops D2 (D20, D21, . . . , D2M−1) receives one bit of an enable control signal, and the output of each second D-type flip-flop is directed to the input of a second D-type flip-flop of a next stage. For example, the output of the flip-flop D20 is coupled to the input of a flip-flop D21, which is the next stage of the flip-flop D20. Each one of multiplexers MUX (MUX0, MUX1, . . . , or MUXM−1) has two input terminals, while one of which is connected to the output of a corresponding D-type flip-flop so as to receive the input data received by relative first D-type flip-flops. For example, the flip-flop D10 will direct the input data it received to the first multiplexer MUX0. Additionally, each multiplexer further has an enable control signal receiving terminal connected to the output of a corresponding second D-type flip-flop, used for receiving an enable control signal received by the second D-type flip-flop. For example, the first multiplexer MUX0 connected to a first second D-type flip-flop D20 will receive an enable control signal delivered from the flip-flop D20. One of D-type latches DG (DG0, DG1, . . . , DGM−1) connects to a corresponding multiplexer so as to output the data selected by the corresponding multiplexer, and the output data is fed back to another input terminal of the corresponding multiplexer, which is also taken as feedback data so as to be selected for data output when a next set of input data are input. For example, a first D-type latch DG0 connected to a first multiplexer MUX0 outputs the data selected by the first multiplexer MUX0, and feeds back its output data to another input terminal of the first multiplexer MUX0. As shown in FIG. 4B, M first D-type flip-flops D1 (D10, D11, . . . , D1M−1) are combined to form a first shift register 410, while M second D-type flip-flops D2 (D20, D21, . . . , D2M−1) are combined to form a second shift register 420.

#A method for serial to parallel of an I/O circuit of the present invention is as follows. First a clear signal CLR is asserted to all first D-type flip-flops D1 (D10, D11, . . . , D1M−1) and all second D-type flip-flops D2 (D20, D21, . . . , D2M−1), respectively, so as to clear out previously input signals stored therein. At which time the data in all the first D-type flip-flop D1 (D10, D11, . . . , D1M−1) are each null, the enable control signals in all the second D-type flip-flops D2 (D20, D21, . . . , D2M−1) are each of a low level (0), therefore the system will select to keep the original output status. A truth table related to operation of one of the multiplexers is as shown in FIG. 8. When the enable control signal is of a high level (1), a multiplexer selects the input data as its output, and when the enable control signal is of a low level (0), the multiplexer selects the feedback data as its output. Next, an N-bit input data stream I (I0 . . . IN−3IN−2IN−1) and an N-bit enable control signal stream E (E0 . . . EN−3EN−2EN−1) are input simultaneously. The input data stream I and the enable control signal E are input into the flip-flop D11 and the flip-flop D20, respectively, one bit each time according to the bit sequence, and the two signals are controlled by a clock signal CLK simultaneously.