Structure for testing an operation of integrated circuitry

A hardware description language (“HDL”) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system, generate a machine-executable representation of integrated circuitry, wherein the HDL design structure comprises:

• a first element processed to generate a functional computer-simulated representation of a general purpose computational resource for performing general purpose operations;
• and
• a second element processed to generate a functional computer-simulated representation of a special purpose computational resource, coupled to the general purpose computational resource, for:
• storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry, wherein the test patterns specify an expected value of the simulated operation;
• executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns;
• determining whether the expected value is different from a measured value of the simulated operation;
• and
• modifying the test patterns in response to a determination that the expected value is different from the measured value.

A method in a computer-aided design system for generating a functional design model of integrated circuitry, the method comprising:

• generating a functional computer-simulated representation of a general purpose computational resource for performing general purpose operations;
• and
• generating a functional computer-simulated representation of a special purpose computational resource, coupled to the general purpose computational resource, for:
• storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry, wherein the test patterns specify an expected value of the simulated operation;
• executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns;
• determining whether the expected value is different from a measured value of the simulated operation;
• and
• modifying the test patterns in response to a determination that the expected value is different from the measured value.