Methods and apparatus for determining a switching history time constant in an integrated circuit device

An article of manufacture for inline measurement of at least one switching history time constant in an integrated circuit device, comprising non-transitory machine readable storage medium with one or more programs stored therein for causing a computer processor to perform the steps of:

• transmitting a series of pulses into a first stage of a delay chain, the delay chain comprising a plurality of delay stages connected together in series and having a length greater than a decay length an initial one of the series of pulses, such that the initial one of the series of pulses does not appear at a second stage of the delay chain;
• determining an amount of time between the transmitting of the initial one of the series of pulses and an initial appearance of the series of pulses at the second stage of the delay chain, wherein the initial appearance of the series of pulses at the second stage of the delay chain comprises an appearance at the second stage of the delay chain of one of the series of pulses other than the initial one of the series of pulses;
• and
• calculating the at least one switching history time constant as a function of a number of stages between the first stage and the second stage, the determined amount of time, and the decay length of the initial one of the series of pulses, based at least in part on a switching history of the integrated circuit device.

An integrated circuit device comprising:

• a delay chain comprising a plurality of delay stages connected in series;
• pulse generation circuitry electrically connected with the delay chain to transmit a series of pulses into a first stage of the delay chain, the delay chain having a length greater than a decay length of an initial one of the series of pulses, such that the initial one of the series of pulses does not appear at a second stage of the delay chain;
• and
• signal delay measurement circuitry electrically connected with the delay chain to determine an amount of time between the transmitting of the initial one of the series of pulses and an initial appearance of the series of pulses at the second stage of the delay chain, wherein the initial appearance of the series of pulses at the second stage of the delay chain comprises an appearance at the second stage of the delay chain of one of the series of pulses other than the initial one of the series of pulses.

A design structure embodied in non-transitory machine readable storage medium, the design structure comprising:

• a delay chain comprising a plurality of delay stages connected in series;
• pulse generation circuitry electrically connected with the delay chain to transmit a series of pulses into a first stage of the delay chain, the delay chain having a length greater than a decay length of an initial one of the series of pulses, such that the a initial one of the series of pulses does not appear at a second stage of the delay chain;
• and
• signal delay measurement circuitry electrically connected with the delay chain to determine an amount of time between the launching transmitting of the initial one of the series of pulses and an initial appearance of the series of pulses at the second stage of the delay chain, wherein the initial appearance of the series of pulses at the second stage of the delay chain comprises an appearance at the second stage of the delay chain of one of the series of pulses other than the initial one of the series of pulses.