Synchronizing apparatus, synchronizing method, synchronizing program and data reproduction apparatus

A synchronizing apparatus for controlling, by a Phase Locked Loop (PLL) circuit, a sampling clock to be used to sample input data and synchronizing a phase of said sampling clock with a target phase that is desirable for sampling said input data, said synchronizing apparatus comprising:

• phase error detection means for detecting a phase error from sampling data and said sampling clock, said sampling data being sampled from said input data at timing of said sampling clock;
• frequency error detection means for detecting a frequency error based on a differential coefficient obtained as a result of detecting said phase error;
• and
• frequency correction means for correcting a frequency of said sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of said PLL circuit, said frequency correction value being calculated based on said frequency error,
• wherein said phase error detection means detects said phase error using said sampling data corresponding to a part where a tentatively determined pattern matches a predetermined data pattern, said tentatively determined pattern being generated by comparing said sampling data with a predetermined level to tentatively determine a code and then arranging tentatively determined results in order of time.

A synchronizing apparatus for controlling, by a Phase Locked Loop (PLL) circuit, a sampling clock to be used to sample input data and synchronizing a phase of said sampling clock with a target phase that is desirable for sampling said input data, said synchronizing apparatus comprising:

• phase error detection means for detecting a phase error from sampling data and said sampling clock, said sampling data being sampled from said input data at timing of said sampling clock;
• frequency error detection means for detecting a frequency error based on a differential coefficient obtained as a result of detecting said phase error;
• and
• frequency correction means for correcting a frequency of said sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of said PLL circuit, said frequency correction value being calculated based on said frequency error,
• wherein said PLL circuit is an Interpolated Timing Recovery (ITR) circuit to perform interpolation on said sampling data by performing, by a predetermined interpolation filter, convolution on said sampling data and a predetermined tap coefficient and control, based on said phase error, phase of said sampling clock by a feedback loop;
• and
• said PLL circuit includes a tap coefficient generation means for generating said tap coefficient of said interpolation filter using a transformed value, said transformed value being generated by transforming an axis of a target frequency characteristic to be used to equalize said input data from a frequency axis to a time axis.