Serial digital data communication interface for transmitting data bits each having a width of multiple clock cycles

A data receiver for receiving a serial communication of binary signals in a frame from a data transmitter, said frame including one or more header bits and one or more data bits, and for decoding the received binary signals into binary data to determine the bits that were transmitted, comprising:

• a clock generator which provides a clock signal of a predetermined clock rate to the transmitter over a clock channel;
• a synchronization signal source which provides to the transmitter over a synchronization channel a synchronization signal for initiating a frame;
• and
• a state machine that receives the serial communication over a data channel, detects a first header bit of the header code a plurality of times, determines data bit sampling times for sampling the serial communication to decode the data bits thereof, and samples at the data bit sampling times, the logic level of the received serial communication and provides corresponding data bit values,
• wherein the state machine determines data bit sampling times by selecting a sampling time from among a finite plurality of potential sample times according to the plurality of times of detection of the first header bit, to sample proximate the nominal middle of a received bit value, and
• wherein the state machine is adapted to sample the received serial communication at the predetermined clock rate, count the number of detections of the first header bit, and determine therefrom the data bit sampling times based on one of two rules:
• sampling at the times corresponding to a second detection of the first header bit, and sampling at the times corresponding to a second to last detection of the first header bit.

A data receiver, comprising:

• a clock generator to provide a clock signal at a predetermined clock rate to a data transmitter;
• and
• a receiver circuit for serial communication of binary signals in a frame from the data transmitter, the frame including one or more header bits and one or more data bits, the receiver circuit to:
• sample logic levels periodically based on the predetermined clock cycle,
• detect a first header bit at a plurality of sampling times,
• determine data bit sampling times for sampling a remainder of the frame, and
• sample logic levels of the rest of the received serial communication at the determined data bit sampling times to provide corresponding data values,
• wherein the data bit sampling times are selected to sample at an estimated middle portion of a received bit, and
• wherein to detect the first header bit, the receiver circuit is configured to sample the received serial communication at the predetermined clock rate, count the number of detections of the first header bit, and determine therefrom the data bit sampling times based on one of two rules:
• sampling at the times corresponding to a second detection of the first header bit, and sampling at the times corresponding to a second to last detection of the first header bit.