Apparatus and method for transferring a signal from a fast clock domain to a slow clock domain

A circuit for capturing a pulse transferred from a fast clock domain to a slow clock domain comprising:

• a set-reset element, disposed in the fast clock domain, for detecting an input pulse and setting a capture period upon detection of the input pulse,
• a first synchronizer, disposed in the slow clock domain, for synchronizing to the detected input pulse, after setting of the capture period, and responsively providing an output pulse,
• a second synchronizer, disposed in the fast clock domain, for synchronizing to the first synchronizer and responsively providing an acknowledgment signal,
• wherein the set-reset element uses the acknowledgement signal for resetting the capture period,
• an external inhibitor prevents the input pulse to be transferred to the fast clock domain, and
• the acknowledgement signal is provided to the external inhibitor for enabling the input pulse to be transferred to the fast clock domain.

A method of capturing a pulse, sent by a fast clock domain and received by a slow clock domain, comprising the steps of:

• setting a time period, by the fast clock domain, upon detection of an input pulse;
• notifying the slow clock domain, by the fast clock domain, of the set time period;
• generating an output pulse, by the slow clock domain, in synchronism to the input pulse, upon notification of the set time period;
• acknowledging to the fast clock domain, by the slow clock domain, of synchronism to the input pulse;
• resetting the time period, by the fast clock domain, upon receipt of the acknowledgment from the slow clock domain;
• sending, by the fast clock domain, an Acknowledge Out signal to an external circuit;
• and
• disabling the input pulse to the fast clock domain, by the external circuit, until receiving the Acknowledge Out signal from the fast clock domain.