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US 8,027,394 B2Granted
Reducing data stream jitter during deinterleaving
AssigneeSilicon Laboratories Inc.
InventorFrederić Nicolas
Life of this patent
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Abstract
In one embodiment, the present invention includes a deinterleaver having an input interface to receive orthogonal frequency division multiplexing (OFDM) symbols from a demodulator, a memory coupled to the input interface to store the OFDM symbols, an output interface coupled to the memory to receive the OFDM symbols stored in the memory, and a digital phase lock loop (PLL) to control and adjust a reading rate of data from the memory responsive to dynamic and static channel conditions.
Claims23
A deinterleaver comprising:
- an input interface to receive orthogonal frequency division multiplexing (OFDM) symbols from a demodulator;
- a memory coupled to the input interface to store the OFDM symbols received from the input interface;
- an output interface coupled to the memory to receive the OFDM symbols stored in the memory;
- and
- a digital phase lock loop (PLL) coupled to the input interface and the output interface, the digital PLL to control and adjust a reading rate of the output interface responsive to dynamic and static channel conditions of a channel that transmits the OFDM symbols.
2 more elements
A method comprising:
- writing symbol data of a first parity into a memory using sequential addressing and writing symbol data of a second parity into the memory using pseudo random addressing;
- reading symbol data of the first parity from the memory using the pseudo random addressing and reading symbol data of the second parity from the memory using the sequential addressing;
- reading symbol data of a first symbol from the memory after all of the symbol data of the first symbol is written into the memory, wherein symbol data of a second symbol is written into the memory while reading the symbol data of the first symbol, and
- initiating a reading rate for reading the symbol data of the first symbol at a first frequency upon writing of a last symbol data of the first symbol into the memory, the first frequency based on a sum of a number of carriers for a demodulator and a number of carriers for a guard interval.
1 more element
A system comprising:
- a tuner to receive a radio frequency (RF) signal from a signal source, and downconvert the RF signal to a second frequency to extract a signal channel from the RF signal;
- a demodulator coupled to the tuner to demodulate the signal channel;
- a forward error correction (FEC) circuit coupled to the demodulator to receive the demodulated signal channel and to generate a transport stream therefrom, the FEC circuit including a front end stage, a decoding stage and a back end stage, wherein the front end stage includes a digital phase lock loop (PLL) coupled to a memory to store demodulated symbol data, the digital PLL to control and adjust a reading rate from the memory responsive to dynamic and static channel conditions of the system;
- and
- a processor coupled to the FEC circuit to receive the transport stream and to process the transport stream to obtain audio visual data.
2 more elements
Dependencies are inferred from the claim text.