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US 8,027,221 B2Granted
Memory device
AssigneeFujitsu Limited
InventorsJin Abe, Osamu Ishibashi, Yoshinori Mesaki
Life of this patent
Estimating the term…
Abstract
A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detection result of the power-supply voltage detector, in synchronization with a rising edge or falling edge of a clock signal; and a memory cell array that performs reading/writing at the data rates set by the data-rate setter.
Claims20
A memory device comprising:
- a voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected;
- a data-rate setter that sets data rates corresponding to the detection result of the voltage detector, in synchronization with a rising edge or falling edge of a clock signal;
- and
- a memory cell array that reads/writes at the data rates set by the data-rate setter.
1 more element
A memory device comprising:
- a voltage detector;
- a data rate setter;
- a clock adjuster;
- and
- a memory cell array;
- wherein
- the voltage detector is connected to a power supply voltage;
- the data rate setter is connected to the voltage detector and the clock adjuster;
- and
- the clock adjuster is connected to the memory cell array.
7 more elements
A memory device comprising:
- a voltage detecting circuit;
- a data rate setting circuit connected to the voltage detecting circuit, able to set different read/write speeds of a memory cell array;
- and
- a memory cell array connected to the data rate setting circuit.
1 more element
Dependencies are inferred from the claim text.