Bit line voltage control in spin transfer torque magnetoresistive random access memory
AssigneeQUALCOMM Incorporated
InventorsSei Seung Yoon, Seung H. Kang
Life of this patent
Estimating the term…
Abstract
A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamping circuit is coupled to the bit line and is configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level. The desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM.
Claims19
A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), comprising:
- a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line;
- a clamping circuit coupled to the bit line, the clamping circuit being configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level, wherein the desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM;
- and
- a read isolation element interposed between the bit cell and the clamping circuit, the isolation element being configured to selectively isolate the clamping circuit from the bit line during a write operation.
A method for reading a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), comprising:
- initiating a read operation;
- activating a clamping circuit coupled to a bit line of a bit cell being read;
- and
- clamping a bit line voltage to a desired voltage level during the read operation, wherein the desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM, and wherein the clamping circuit is selectively isolated from the bit line during the write operation.
A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), comprising:
- means for initiating a read operation of a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line;
- means for clamping a bit line voltage to a desired voltage level during the read operation, wherein the desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM;
- and
- means for selectively isolating the clamping circuit from the bit line during the write operation.
Dependencies are inferred from the claim text.