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US 8,027,201 B2Granted
Nonvolatile memory device with load-free wired-or structure and an associated driving method
AssigneeSamsung Electronics Co., Ltd.
InventorSeung-Jae Lee
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal output line, and a data input line physically distinct from the internal output line, and configured to pull the internal output line to an output drive voltage in response to a bitline voltage on one of the bitlines coupled to the page buffer.
Claims12
A method of operating a semiconductor memory device, comprising:
- precharging each of a plurality of sensing nodes with a precharge voltage;
- coupling a bitline having an associated bitline voltage to each sensing node;
- comparing each of the bitline voltages with the precharge voltage of the corresponding sensing node;
- combining the comparisons;
- and
- indicating a failure to program in response to the combination,
- wherein combining the comparisons comprises:
- pulling an internal output line to an output drive voltage when the comparing indicates a substantial difference between the bitline voltage and the sensing node corresponding to the internal output line;
- precharging a global output line;
- and
- coupling the global output line to the internal output line.
8 more elements
A nonvolatile semiconductor memory device comprising:
- means for precharging each of a plurality of sensing nodes with a precharge voltage;
- means for coupling a bitline having an associated bitline voltage to each sensing node;
- means for comparing each of the bitline voltages with the precharge voltage of the corresponding sensing node;
- means for combining the comparisons;
- and
- means for indicating a failure to program in response to the combination,
- wherein the means for combining the comparisons comprises:
- means for pulling an internal output line to an output drive voltage when the comparing indicates a substantial difference between the bitline voltage and the sensing node corresponding to the internal output line;
- means for precharging a global output line;
- and
- means for coupling the global output line to the internal output line.
8 more elements
A method of operating a semiconductor memory device, comprising:
- precharging a plurality of sensing nodes with a precharge voltage, the plurality of sensing nodes corresponding to a plurality of page buffers;
- coupling bitlines having associated bitline voltages to the plurality of sensing nodes, respectively;
- setting states of a plurality of main latch blocks in response to corresponding signals on the plurality of sensing nodes, respectively;
- providing output signals from internal output lines of the plurality of page buffers in response to the set states of the plurality of main latch blocks, respectively;
- combining the internal output line outputs of the plurality of page buffers;
- and
- verifying a program operation of the semiconductor memory device based on the combined internal output line outputs.
4 more elements
Dependencies are inferred from the claim text.