Folding data stored in binary format into multi-state format within non-volatile memory devices

A method of operating a non-volatile memory system including a non-volatile memory circuit having an array of non-volatile memory cells formed along a plurality of word lines and a plurality of bit lines, the bit lines forming a plurality of subsets each connectable to a corresponding set of data registers, the method comprising:

• reading data stored in an N-bit per cell format from a first plurality of memory cells along a first of the word lines, where N is greater than one and the first plurality of memory cells are formed along a corresponding first plurality of bit lines;
• storing the N-bit per cell data read from each of the first plurality of memory cells into a first register of the set of registers corresponding to the first plurality of bit lines;
• rearranging the data from each of the first registers in N other registers with the same set of registers;
• and
• transferring out the data from the N other registers of the set of registers corresponding to the first plurality of bit lines in the order in which the data was received on the memory prior to being stored thereon.

A method of operating a non-volatile memory system including a controller circuit and non-volatile memory circuit having an array of non-volatile memory cells formed along a plurality of word lines and a plurality of bit lines, the method comprising:

• receiving data at the controller;
• generating within the controller a corresponding error correction code for the data;
• transferring the data and the corresponding error correction code to the memory;
• writing the data and the corresponding error correction code along a first of the word lines in a binary format;
• within the memory, subsequently rewriting the data and the corresponding error correction code along a second of the words lines in a multi-state format, where the corresponding error correction code is generated dependent upon how the data is arranged into multistate format.

A non-volatile memory circuit, comprising:

• a memory array having a plurality of non-volatile memory cells formed along a plurality of word lines and a plurality of bit lines;
• read circuitry connectable to the memory array, including a plurality of sense amps, each connectable to one or more of the bit lines to perform a binary read operation;
• write circuitry connectable to the memory array to perform a multi-state program operation;
• and
• a data register stack accessible to the read circuitry and the write circuitry, including:
• a first register connectable to receive the output of the sense amp to receive and hold the output of a binary sensing operation on a first of the word lines from N or more bit lines, N being an integer greater than one;
• N second registers connectable to the first register for the transfer of content therebetween;
• and
• processing circuitry connectable to the first and second register, whereby values corresponding to the output of N binary sensing operations on the first word line held in the first register can each be transferred to a corresponding one of the N second registers for use in an N-bit per cell programming operation of a cell on a second of the word lines.