Semiconductor memory device having bit line disturbance preventing unit
AssigneeSamsung Electronics Co., Ltd.
InventorHyun-Bae Lee
Life of this patent
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Abstract
A read data path circuit for use in the semiconductor memory device includes a bit line sense amplifier, a local input/output line sense amplifier, a column selection unit operationally coupling a bit line pair with the local input/output line pair in response to a column selection signal, where the bit line pair is coupled to the bit line sense amplifier and the local input/output line pair is coupled to the local input/output line sense amplifier, and a bit line disturbance preventing unit configured to equalize signal levels of the local input/output line pair before the column selection signal is activated, and configured to sense and amplify signal levels of bit line data transferred to the local input/output line pair after the column selection signal is activated.
Claims20
A read data path circuit for use in a semiconductor memory device, the circuit comprising:
- a bit line sense amplifier;
- a local input/output line sense amplifier;
- a column selection unit operationally coupling a bit line pair with the local input/output line pair in response to a column selection signal, where the bit line pair is coupled to the bit line sense amplifier and the local input/output line pair is coupled to the local input/output line sense amplifier;
- and
- a bit line disturbance preventing unit configured to equalize signal levels of the local input/output line pair before the column selection signal is activated, and configured to sense and amplify signal levels of bit line data transferred to the local input/output line pair after the column selection signal is activated.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells, each memory cell including an access transistor and a storage capacitor;
- a bit line pair coupled with the memory cells;
- a bit line sense amplifier coupled to the bit line pair;
- a local input/output line sense amplifier coupled to the local input/output line pair;
- a column selection unit operationally coupling the bit line pair with the local input/output line pair in response to a column selection signal, where the bit line pair is coupled to the bit line sense amplifier and the local input/output line pair is coupled to the local input/output line sense amplifier;
- and
- a bit line disturbance preventing unit configured to equalize the local input/output line pair without precharging the local input/output line pair before the column selection signal is activated.
A read data path circuit for use in a semiconductor memory device, comprising:
- a disturbance preventing unit including a transmission gate, where the transmission gate includes,
- a first PMOS transistor having a gate receiving a local input/output line equalizing signal, a source coupled to one of first and second local input/output lines of a local input/output line pair, and a drain coupled to another of the first and second local input/output lines of the local input/output line pair, where the first PMOS transistor is configured to equalize a potential of the local input/output line pair to a same level before the column selection signal is activated, and
- a first NMOS transistor having a gate receiving an inverted signal of the local input/output line equalizing signal, a drain coupled to one of first and second local input/output lines of the local input/output line pair, and a source coupled to another of the first and second local input/output lines of the local input/output line pair, where the first NMOS transistor is configured to equalize a potential of the local input/output line pair to a same level before the column selection signal is activated.
Dependencies are inferred from the claim text.