Command processing circuit and phase change memory device using the same

A command processing circuit for generating internal command signals corresponding to a plurality of unit internal command signals sequentially applied during a plurality of command cycles, the command processing circuit comprising:

• a first command latching unit configured to latch a first unit internal command signal applied in a first command cycle;
• and
• a second command latching unit configured to latch a second unit internal command signal in response to the first unit internal command signal latched in the first command latching unit in a second command cycle after the first command cycle, and output an internal command signal corresponding to the first unit internal command signal and the second unit internal command signal,
• wherein the first and second command latching units are configured to latch the unit internal command signals applied in the corresponding command cycles and further configured to not latch a signal applied to the respective latching unit when a predefined signal is in a latched state within the respective latching unit.

A phase change memory device, which receives command sequences applied during a plurality of command cycles, the command sequences including a plurality of unit command codes corresponding to a respective command cycle, and generates internal command signals corresponding to the command sequences, the phase change memory device comprising:

• a first decoding unit configured to decode unit command codes sequentially applied from outside of the phase memory device to output unit internal command signals corresponding to the unit command codes;
• a second decoding unit configured to decode command control codes applied from the outside to output an internal control signal corresponding to the unit command codes;
• and
• a command processing unit configured to latch, in response to the internal control signal, unit internal command signals corresponding to those of the unit command codes that are commonly contained in the command sequences, in common command latching units, and latch unit internal command signals corresponding to the unit command sequences contained only in the corresponding command sequences among the plurality of command sequences, in command latching units allocated to the corresponding command sequences, and output the plurality of internal command signals corresponding to the signals latched in the common command latching units and the signals latched in the command latching units allocated to the command sequences.