Driving method, driving circuit and driving apparatus for a display system
AssigneeTrident Microsystems (Far East) Ltd.
InventorRob Anne Beuker
Life of this patent
Estimating the term…
Abstract
A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.
Claims18
Method of operating a driving circuit for a display system, wherein the sequence of writing and/or reading video data into and/or from a memory is controlled by means of an address sequencer, each of the memory addresses for said video data generated in the address sequencer being composed of a picture line address part or line pointer and an address part for a pixel on said picture line, the method comprising:
- storing a full table of line pointers for different sequences of video data to be displayed in the memory;
- and
- operating the driving circuit in an address sequence mode wherein the address sequencer generates addresses for the video data in the memory by combining line pointers that are read out by a line counter from a block of line pointers in address table register means with the output of a pixel counter using an adder, and in a table update mode wherein a block of line pointers from the full table of line pointers that is stored in said memory is downloaded into said address table register means, wherein operating the driving circuit in the table update mode includes:
- setting a base address of the block of line pointers to zero;
- reading a line pointer that corresponds to the base address of zero from the memory into the address table register means;
- and
- successively increasing the base address by one and reading the corresponding line pointer from the memory into the address table register means until the last line pointer of the block of line pointers is downloaded into the address table register means.
Driving circuit for a display system comprising:
- a memory for video data to be displayed and coupled thereto an address sequencer for controlling the sequence of writing and/or reading the video data in said memory, characterized in that the memory contains a full table of line pointers, each line pointer being part of a memory address for video data, and in that the address sequencer is provided with address table register means for a block of line pointers from said table of line pointers;
- means for successively updating the address table register means with subsequent blocks of line pointers from the full table of line pointers that is contained in the memory, wherein the means for successively updating the address table register means with the subsequent blocks of line pointers is configured to set a base address of a block of line pointers to zero, to read a line pointer that corresponds to the base address of zero from the memory into the address table register means, to successively increase the base address by one and to read the corresponding line pointer from the memory into the address table register means until the last line pointer of the block of line pointers is downloaded into the address table register means;
- a pixel counter, the output of which in combination with the consecutive line pointers that are read out by a line counter from the address table register means using an adder determines the addresses for said video data;
- and
- switching means, by which memory addresses for video data are generated in an address sequence mode in the address sequencer, and in a table update mode the address table register is updated with a next block of line pointers from the full table of line pointers that is contained in the memory.
Driving circuit for a display system comprising:
- a memory for video data to be displayed and coupled thereto an address sequencer for controlling the sequence of writing and/or reading the video data in said memory, characterized in that the memory contains a full table of line pointers for different sequences of video data to be displayed, each line pointer being part of a memory address for video data, and in that the address sequencer is provided with address table register means for a block of line pointers from said table of line pointers;
- means for successively updating the address table register means with subsequent blocks of line pointers from the full table of line pointers that is contained in the memory, wherein the means for successively updating the address table register means with the subsequent blocks of line pointers is configured to set a base address of a block of line pointers to zero, to read a line pointer that corresponds to the base address of zero from the memory into the address table register means, to successively increase the base address by one and to read the corresponding line pointer from the memory into the address table register means until the last line pointer of the block of line pointers is downloaded into the address table register means;
- and
- a pixel counter, the output of which in combination with the consecutive line pointers that are read out by a line counter from the address table register means using an adder determines the addresses for said video data.
Dependencies are inferred from the claim text.