Liquid crystal display having gate delay compensator

A driving method for a liquid crystal display, the liquid crystal display comprising a scanning driver, a liquid crystal panel, and a compensator, the liquid crystal panel comprising a plurality of gate lines G1˜G2n, the compensator comprising a plurality of switching elements corresponding to the plurality of the gate lines one to one, each switching element being connected to an end of the gate line G1 distal from the scanning driver, where n is a natural number, 1≦i≦2n, and i is a natural number, the method comprising the following:

• when the scanning driver applies a high scanning voltage to the gate line Gi, the compensator applies a high compensating voltage to the end of the gate line Gi distal from the scanning driver, and
• when the scanning driver applies a high scanning voltage to the gate line Gi+1, the scanning driver applies a low voltage to the gate line Gi, and the compensator applies a low compensating voltage to the end of the gate line Gi distal from the scanning driver,
• wherein the high compensating voltage and the low compensating voltage are applied to the end of the gate line Gi distal from the scanning driver through the same switching element which is connected to the tail end of the gate line Gi;
• wherein the switching element comprises a second thin film transistor, the second thin film transistor comprising a gate electrode, a source electrode and a drain electrode, the gate electrode of the second thin film transistor being directly connected to the source electrode, the source electrode of the second thin film transistor being connected to the tail end of the gate line Gi, and the drain electrode of the second thin film transistor configured to receive the high compensating voltage and the low compensating voltage.

A liquid crystal display comprising:

• a liquid crystal panel comprising a plurality of gate lines G1˜G2n parallel to each other, a plurality of data lines parallel to each other and intersecting the gate lines G1˜G2n, each of the gate lines G1˜G2n comprising a front end and a tail end, where n is a natural number;
• a plurality of first thin film transistors arranged at each intersection of the gate line and the data line, a gate electrode of each first TFT being connected to the corresponding gate line Gi, where 1≦i≦2n, and i is a natural number;
• a scanning driver configured for scanning the gate lines G1˜G2n in sequence, the scanning driver being connected to the front ends of the gate lines G1˜G2n;
• a data driver configured for providing a plurality of gray scale voltages to the data lines;
• and
• a compensator configured for compensating the scanning signals,
• wherein when the scanning driver applies a high scanning voltage to the gate line Gi to turn on the first thin film transistors connected the gate line Gi, the compensator applies a high compensating voltage to the tail end of the gate line Gi to accelerate to turn on the first thin film transistors adjacent to the tail end of the gate line Gi;
• and
• when the scanning driver applies a high scanning voltage to the gate line Gi+1 to turn on the first thin film transistors connected the gate line Gi+1, the scanning driver applies a low voltage to the gate line Gi to turn off the first thin film transistors connected the gate line Gi, and the compensator applies a low compensating voltage to the tail end of the gate line Gi to accelerate to turn off the first thin film transistors adjacent to the tail end of the gate line Gi,
• wherein the compensator comprises a plurality of switching elements corresponding to the plurality of the gate lines one to one, each switching element is connected to the tail end of the corresponding gate line Gi, and the high compensating voltage and the low compensating voltage are applied to the tail end of the gate line Gi through the same switching element which is connected to the tail end of the gate line Gi;
• wherein the switching element comprises a second thin film transistor, the second thin film transistor comprising a gate electrode, a source electrode and a drain electrode, the gate electrode of the second thin film transistor being directly connected to the source electrode, the source electrode of the second thin film transistor being connected to the tail end of the gate line Gi, and the drain electrode of the second thin film transistor configured to receive the high compensating voltage and the low compensating voltage.