Device for safe data transmission to railway beacons

A device (1) for safe data transmission to railway beacons, characterized by comprising a first and a second circuit section (1a, 1b) independent of and galvanically separate from each other, and each comprising:

• a microprocessor (6a, 6b) selection stage (2a, 2b) configured to receive information signals relative to the status of a portion of a railway line, and to generate at least one telegram for transmission to a beacon;
• and
• a control stage (3a, 3b) configured to compare the telegrams generated by the first and second circuit section (1a, 1b) for enabling/disabling data transmission to said beacon;
• said first circuit section (1a) also comprising a transmission enabling stage (4, 5, 17), configured to allow transmission to said beacon of the telegram generated by said first circuit section (1a), in the event the comparison performed by said control stage (3a, 3b) is successful;
• wherein said transmission enabling stage (4, 5, 17) comprises an optoisolating circuit (17) interposed between the control stage (3a) of said first circuit section (1a) and said beacon;
• said optoisolating circuit (17) cooperating with a watchdog circuit (18), which receives signals from the microprocessors (6a, 6b) of said first and said second circuit section (1a, 1b) to disable said optoisolating circuit (17) in the event said comparison by said control stage (3a, 3b) is unsuccessful.

A device (1) for safe data transmission to railway beacons, characterized by comprising a first and a second circuit section (1a, 1b) independent of and galvanically separate from each other, and each comprising:

• a microprocessor (6a, 6b) selection stage (2a, 2b) configured to receive information signals relative to the status of a portion of a railway line, and to generate at least one telegram for transmission to a beacon;
• and
• a control stage (3a, 3b) configured to compare the telegrams generated by the first and second circuit section (1a, 1b) for enabling/disabling data transmission to said beacon;
• said first circuit section (1a) also comprising a transmission enabling stage (4, 5, 17), configured to allow transmission to said beacon of the telegram generated by said first circuit section (1a), in the event the comparison performed by said control stage (3a, 3b) is successful;
• wherein said control stage (3a, 3b) comprises:
• at least one EXOR logic gate (20a-20d) receiving the telegrams generated by the microprocessors (6a, 6b) of the first and second circuit section (1a, 1b) respectively;
• an error counter (21a-21d) having an input connected to the output of said EXOR logic gate (20a-20d);
• and
• an error location detector (22a-22d) having an input connected to the output of said error counter (21a-21d), and generating a control signal which is sent to the respective microprocessor (6a, 6b).

A device (1) for safe data transmission to railway beacons, characterized by comprising a first and a second circuit section (1a, 1b) independent of and galvanically separate from each other, and each comprising:

• a microprocessor (6a, 6b) selection stage (2a, 2b) configured to receive information signals relative to the status of a portion of a railway line, and to generate at least one telegram for transmission to a beacon;
• and
• a control stage (3a, 3b) configured to compare the telegrams generated by the first and second circuit section (1a, 1b) for enabling/disabling data transmission to said beacon;
• said first circuit section (1a) also comprising a transmission enabling stage (4, 5, 17), configured to allow transmission to said beacon of the telegram generated by said first circuit section (1a), in the event the comparison performed by said control stage (3a, 3b) is successful;
• wherein each said selection stage (2a, 2b) generates a number of telegrams for transmission to respective beacons;
• said selection stage (2a, 2b) forming an overall telegram comprising a number of groups of successive bits, each group comprising bits having corresponding locations in the various telegrams;
• and said control stage (3a, 3b) comprising a demultiplexer circuit (12a, 12b), which receives said overall telegram and transmits the various bits in each group to respective outputs (OUT1a/b, OUT2a/b, OUT3a/b, OUT4a/b) so that the respective telegram is reconstructed at each output (OUT1a/b, OUT2a/b, OUT3a/b, OUT4a/b).