Relaxation oscillator
AssigneeSynaptics Incorporated
InventorShahrooz Shahparnia
Life of this patent
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Abstract
The relaxation oscillator includes a comparator and a latch. The comparator includes a comparator output and a comparator input that is configured to receive a first input signal in response to a first signal and configured to receive a second input signal in response to a second signal. The latch includes a latch-set input that is configured to be coupled to the comparator output in response to a third signal, a latch-reset input that is configured to be coupled to the comparator output in response to a fourth signal and a latch output that is configured to output the second signal. The relaxation oscillator is configured to achieve an approximately fifty percent duty cycle without requiring the use of a second comparator.
Claims20
A relaxation oscillator comprising:
- a comparator comprising:
- a comparator input configured to receive a first input signal in response to a first signal and configured to receive a second input signal in response to a second signal;
- and
- a comparator output;
- a latch comprising:
- a latch-set input configured to be coupled to said comparator output in response to a third signal;
- a latch-reset input configured to be coupled to said comparator output in response to a fourth signal;
- and
- a latch output configured to output said second signal;
- and
- a fourth switching mechanism, wherein said fourth switching mechanism is configured to couple said latch-reset input to ground when said latch-set input is coupled to said comparator output, and wherein said fourth switching mechanism is configured to couple said latch-set input to ground when said latch-reset input is coupled to said comparator output;
- wherein said relaxation oscillator is configured to achieve an approximately fifty percent duty cycle without requiring use of a second comparator.
A relaxation oscillator comprising:
- a first switching mechanism comprising:
- a first switching mechanism output;
- a first input configured to couple a first input signal to said first switching mechanism output in response to a first signal;
- and
- a second input configured to couple a second input signal to said first switching mechanism output in response to a second signal;
- a comparator comprising:
- a comparator input coupled to said first switching mechanism output;
- and
- a comparator output;
- a second switching mechanism comprising:
- a second switching mechanism input coupled to said comparator output;
- a first output of said second switching mechanism configured to couple to said comparator output in response to a third signal;
- and
- a second output of said second switching mechanism configured to couple to said comparator output in response to a fourth signal;
- a latch comprising:
- a latch-set input coupled to said first output of said second switching mechanism;
- a latch-reset input coupled to said second output of said second switching mechanism;
- and
- a latch output configured to output said second signal;
- and
- a fourth switching mechanism, wherein said fourth switching mechanism is configured to couple said latch-reset input to ground when said first output of said second switching mechanism is coupled to said comparator output, and wherein said fourth switching mechanism is configured to couple said latch-set input to ground when said second output of said second switching mechanism is coupled to said comparator output;
- and
- wherein said relaxation oscillator is configured to achieve an approximately fifty percent duty cycle.
A method for producing a clock signal with an approximately fifty percent duty cycle, said method comprising:
- coupling an input of a comparator to a first input signal in response to a first signal and to a second input signal in response to a second signal;
- comparing said first input signal against a reference voltage;
- generating a first triggering signal on a comparator output of said comparator, in response to said first input signal substantially equaling said reference voltage;
- comparing said second input signal against said reference voltage;
- generating a second triggering signal on said comparator output of said comparator, in response to said second input signal substantially equaling said reference voltage;
- coupling a latch-set input of a latch to said comparator output in response to a third signal,
- coupling a latch-reset input of said latch to said comparator output in response to a fourth signal;
- coupling said latch-reset input of said latch to ground when said latch-set input of said latch is coupled to said comparator output;
- coupling said latch-set input of said latch to ground when said latch-reset input of said latch is coupled to said comparator output;
- and
- generating said second signal on a latch output of said latch in response to said first triggering signal and said second triggering signal;
- wherein said clock signal with an approximately fifty percent duty cycle is produced without requiring use of a second comparator.
Dependencies are inferred from the claim text.