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US 8,026,760 B1Granted
Gain enhanced switched capacitor circuit and method of operation
AssigneeFreescale Semiconductor, Inc.
InventorAmmisetti V. Prasad
Life of this patent
Estimating the term…
Abstract
A switched capacitor circuit utilizes a pair of serially connected differential amplifiers that have plus inputs, minus inputs, plus outputs, and minus outputs. Feedback to the plus/minus inputs is in a first configuration relative to the output of the pair of differential amplifiers in a sampling mode and a second configuration in a hold mode. Similarly, the plus/minus inputs relative to the plus/minus outputs of the serially connected differential amplifiers is reversed between the sampling and hold modes.
Claims20
A method of operating a circuit in response to a pair of differential signals in which the circuit has a first differential amplifier, a second differential amplifier, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, wherein
- a first terminal of the first capacitor is coupled to a plus input of the first differential amplifier;
- a first terminal of the second capacitor is coupled to a minus input of the first differential amplifier;
- a first terminal of the third capacitor is coupled to a minus output of the second differential amplifier;
- a first terminal of the fourth capacitor is coupled to a plus output of the second differential amplifier;
- the method comprising:
- during a sampling mode of the circuit:
- coupling a first signal of the pair of differential signals to a second terminal of the first capacitor;
- coupling a second signal of the pair of differential signals to a second terminal of the second capacitor;
- coupling the plus input of the first differential amplifier to a second terminal of the fourth capacitor;
- coupling the minus input of the first differential amplifier to a second terminal of the third capacitor;
- coupling a plus output of the first differential amplifier to a minus input of the second differential amplifier;
- and
- coupling a minus output of the first differential amplifier to a plus input of the second differential amplifier;
- and
- during a hold mode of the circuit:
- decoupling the first signal from the second terminal of the first capacitor;
- decoupling the second signal from the second terminal of the second capacitor;
- decoupling the plus input of the first differential amplifier from the second terminal of the fourth capacitor;
- decoupling the minus input of the first differential amplifier from the second terminal of the third capacitor;
- decoupling the plus output of the first differential amplifier from the minus input of the second differential amplifier;
- decoupling the minus output of the first differential amplifier from the plus input of the second differential amplifier;
- coupling the second terminal of the first capacitor to the minus output of the second differential amplifier;
- coupling the second terminal of the second capacitor to the plus output of the second differential amplifier;
- coupling the second terminal of the fourth capacitor to a reference terminal;
- coupling the second terminal of the third capacitor to the reference terminal;
- coupling the plus output of the first differential amplifier to the plus input of the second differential amplifier;
- and
- coupling the minus output of the first differential amplifier to the minus input of the second differential amplifier.
25 more elements
A method of operating a circuit in response to a pair of differential signals in which the circuit has a first differential amplifier, a second differential amplifier, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor, wherein
- a first terminal of the first capacitor is coupled to a plus input of the first differential amplifier;
- a first terminal of the second capacitor is coupled to a minus input of the first differential amplifier;
- a first terminal of the third capacitor is coupled to a minus output of the second differential amplifier;
- a first terminal of the fourth capacitor is coupled to a plus output of the second differential amplifier;
- a first terminal of the fifth capacitor is coupled to the plus input of the first differential amplifier;
- and
- a first terminal of the sixth capacitor is coupled to the minus input of the first differential amplifier;
- the method comprising:
- during a sampling mode of the circuit:
- coupling a first signal of the pair of differential signals to a second terminal of the first capacitor;
- coupling a second signal of the pair of differential signals to a second terminal of the second capacitor;
- coupling the plus input of the first differential amplifier to a second terminal of the fourth capacitor;
- coupling the minus input of the first differential amplifier to a second terminal of the third capacitor;
- coupling a plus output of the first differential amplifier to a minus input of the second differential amplifier;
- coupling a minus output of the first differential amplifier to a plus input of the second differential amplifier;
- coupling a second terminal of the fifth capacitor to the reference terminal;
- and
- coupling a second terminal of the sixth capacitor to the reference terminal;
- and
- during the hold mode:
- decoupling the first signal from the second terminal of the first capacitor;
- decoupling the second signal from the second terminal of the second capacitor;
- decoupling the plus input of the first differential amplifier from the second terminal of the fourth capacitor;
- decoupling the minus input of the first differential amplifier from the second terminal of the third capacitor;
- decoupling the plus output of the first differential amplifier from the minus input of the second differential amplifier;
- decoupling the minus output of the first differential amplifier from the plus input of the second differential amplifier;
- decoupling the second terminal of the fifth capacitor from the reference terminal;
- decoupling the second terminal of the sixth capacitor from the reference terminal;
- coupling the first terminal of the of the first capacitor to the reference terminal;
- coupling the first terminal of the of the second capacitor to the reference terminal;
- coupling the second terminal of the fifth capacitor to the minus output of the second differential amplifier;
- and
- coupling the second terminal of the sixth capacitor to the plus output of the second differential amplifier.
30 more elements
A circuit, comprising:
- a first differential amplifier having a plus input, a minus input, a plus output, and a minus output;
- a second differential amplifier having a plus input, a minus input, a plus output, and a minus output;
- a first switch having a first terminal for receiving a first signal of a pair of differential signals and a second terminal, wherein the first switch is open during a hold mode and closed during a sampling mode;
- a first capacitor having a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the plus input of the first differential amplifier;
- a second switch having a first terminal for receiving a second signal of a pair of differential signals and a second terminal, wherein the second switch is open during a hold mode and closed during a sampling mode;
- a second capacitor having a first terminal coupled to the second terminal of the second switch and a second terminal coupled to the minus input of the first differential amplifier;
- a third switch having a first terminal coupled to the minus input of the first differential amplifier and a second terminal, wherein the third switch is open during a hold mode and closed during a sampling mode;
- a fourth switch having a first terminal coupled to the second terminal of the third switch and a second terminal coupled to a reference terminal, wherein the fourth switch is open during the sampling mode and closed during the hold mode;
- a third capacitor having a first terminal coupled to the second terminal of the third switch and a second terminal coupled to the minus output of the second differential amplifier;
- a fifth switch having a first terminal coupled to the first terminal of the first capacitor and a second terminal coupled to the minus output of the second differential amplifier, wherein the fifth switch is closed during a hold mode and open during a sampling mode;
- a sixth switch having a first terminal coupled to the plus input of the first differential amplifier and a second terminal, wherein the sixth switch is open during a hold mode and closed during a sampling mode;
- a seventh switch having a first terminal coupled to the second terminal of the sixth switch and a second terminal coupled to a reference terminal, wherein the seventh switch is closed during a hold mode and open during a sampling mode;
- a fourth capacitor having a first terminal coupled to the second terminal of the sixth switch and a second terminal coupled to the plus output of the second differential amplifier;
- an eighth switch having a first terminal coupled to the first terminal of the second capacitor and a second terminal coupled to the plus output of the second differential amplifier, wherein the eighth switch is closed during a hold mode and open during a sampling mode;
- a ninth switch having a first terminal coupled to the plus output of the first differential amplifier and a second terminal coupled to the minus input of the second differential amplifier, wherein the second switch is open during a hold mode and closed during a sampling mode;
- a tenth switch having a first terminal coupled to the plus output of the first differential amplifier and a second terminal coupled to the plus input of the second differential amplifier, wherein the tenth switch is closed during a hold mode and open during a sampling mode;
- an eleventh switch having a first terminal coupled to the minus output of the first differential amplifier and a second terminal coupled to the plus input of the second differential amplifier, wherein the second switch is open during a hold mode and closed during a sampling mode;
- and
- a twelfth switch having a first terminal coupled to the minus output of the first differential amplifier and a second terminal coupled to the minus input of the second differential amplifier, wherein the twelfth switch is closed during a hold mode and open during a sampling mode.
16 more elements
Dependencies are inferred from the claim text.