Prescaling stage for high frequency applications

A circuit, comprising:

• a supply voltage terminal and a voltage reference terminal;
• a bistable latch circuit having respective master and slave portions coupled between the supply voltage terminal and the voltage reference terminal and feedback coupled to each other, each of the master and slave portions including:
• a differential stage coupled to the supply voltage terminal and including output terminals;
• a differential pair of cross-coupled bipolar transistors coupled to the output terminals of the differential stage;
• a respective transistor stage coupling the differential stage and the differential pair of cross-coupled transistors to the voltage reference terminal, the transistor stage having first and second parallel coupled transistors with common control terminals, the first and second parallel coupled transistors coupled to the respective bipolar transistors in the differential pair of cross-coupled transistors;
• and
• a degeneration capacitance coupled to respective emitter terminals of the bipolar transistors of the differential pair.

A circuit, comprising:

• a prescaling stage that includes:
• a supply voltage terminal and a voltage reference terminal;
• a latch circuit having a differential stage coupled to the supply voltage terminal by a resistive load and having output terminals;
• a differential pair of cross-coupled transistors by coupled to the output terminals of the differential stage;
• a transistor stage coupling the differential stage and the differential pair of cross-coupled transistors to the voltage reference terminal, the transistor stage having first and second transistors in parallel with each other and coupled to the respective transistors in the pair of cross-coupled transistors and to an internal circuit node and having respective control terminals coupled to each other;
• and
• a degeneration capacitance coupled between respective emitter or source terminals of the transistors of the differential pair.

A circuit, comprising:

• a fixed frequency prescaling stage having a high speed and low voltage for high frequency application, the pre-scaling stage including:
• a bistable circuit in turn including respective master and slave portions inserted between a supply voltage and a voltage reference and feedback connected to each other, each of the master and slave portions including:
• a supply voltage terminal and a voltage reference terminal;
• a differential stage having output terminals coupled to the supply voltage terminal;
• a differential pair of cross-coupled transistors, coupled to the output terminals of the differential stage;
• a transistor stage coupling the differential stage and the differential pair of cross-coupled transistors to the voltage reference terminal, the transistor stage having first and second parallel coupled transistors with common control terminals, the first and second parallel coupled transistors coupled to respective transistors in the pair of cross-coupled transistors;
• a degeneration capacitance inserted in correspondence with respective emitter or source terminals of the transistors of the differential pair.

A circuit, comprising:

• a bistable latch circuit having respective master and slave portions coupled between a supply voltage terminal and a voltage reference terminal and feedback coupled to each other, each of the master and slave portions including:
• a differential stage coupled to the supply voltage terminal;
• a resistive load coupled between the differential stage and the supply voltage terminal;
• a differential pair of cross-coupled transistors coupled to the output terminals of the differential stage;
• a degeneration capacitance coupled to respective emitter or source terminals of the transistors of the differential pair and structured to increase a maximum working frequency of the bistable latch circuit;
• and
• a transistor stage coupling the differential stage and the differential pair of cross-coupled transistors to the voltage reference terminal, the transistor stage having first and second transistors coupled in parallel with each other between the differential stage and an internal circuit node and having respective control terminals coupled to each other, the transistor stage further including a third transistor coupled between a first end of the degeneration capacitance and the internal circuit node, as well as a fourth transistor coupled between a second end of the degeneration capacitance and the internal circuit node, the third and fourth transistors having common control terminals.

A prescaling stage, comprising:

• a latch circuit that includes a differential stage coupled to a first voltage terminal by a resistive load and having output terminals;
• a differential pair of cross-coupled transistors coupled to the output terminals of the differential stage;
• a degeneration capacitance coupled between respective emitter or source terminals of the transistors of the differential pair;
• and
• a transistor stage coupling the differential stage and the differential pair of cross-coupled transistors to a second voltage terminal, the transistor stage including first and second transistors coupled in parallel with each other and coupled between the differential stage and an internal circuit node and having respective control terminals coupled to each other, and a third transistor coupled between a first end of the degeneration capacitance and the internal circuit node, as well as a fourth transistor coupled between a second end of the degeneration capacitance and the internal circuit node, the third and fourth transistors having common control terminals.

A system, comprising:

• a bistable circuit that includes respective master and slave portions coupled between a supply voltage terminal and a voltage reference terminal and feedback coupled to each other, each of the master and slave portions including:
• a differential stage coupled by a resistive load to the supply voltage terminal, the differential stage having output terminals;
• a differential pair of cross-coupled transistors coupled to the output terminals of the differential stage;
• a degeneration capacitance coupled in correspondence with respective emitter or source terminals of the transistors of the differential pair;
• and
• a transistor stage coupling the differential stage and the differential pair of cross-coupled transistors to the voltage reference terminal, the transistor stage of each of the master and slave portions having first and second transistors coupled, in parallel with each other, between the differential stage and an internal circuit node and having respective control terminals coupled to each other, a third transistor coupled between a first end of the degeneration capacitance and the internal circuit node, as well as a fourth transistor coupled between a second end of the degeneration capacitance and the internal circuit node, the third and fourth transistors having common control terminals.