Delay circuit
AssigneeHynix Semiconductor Inc.
InventorYun Seok Hong
Life of this patent
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Abstract
Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an input signal. The timing adjusting unit is configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed. The pulse width adjusting unit is configured to adjust a pulse width of the output signal in response to the activation of the output signal.
Claims13
A delay circuit comprising:
- a pulse generating unit configured to generate a pulse signal having a preset width in response to a rising edge of an input signal;
- a timing adjusting unit configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed;
- a pulse width adjusting unit configured to adjust a pulse width of the output signal in response to the activation of the output signal;
- and
- an initialization unit configured to initialize the output signal in response to a control signal, wherein a power up signal is used as the control signal.
The delay circuit of 2, wherein the pulse width adjusting unit comprises:
- a second delay device configured to delay the output of the first delay device for a preset time;
- and
- a second switching device configured to inactivate the output signal in response to an output of the second delay device.
A delay circuit comprising:
- a pulse generating unit configured to generate a pulse signal having a preset width in response to a rising edge of an input signal;
- a first switching device configured to output a voltage in response to the pulse signal;
- a first delay device configured to activate an output signal by delaying an output of the first switching device for a first setting time;
- a second delay device configured to delay an output of the first delay device for a second setting time;
- and
- a second switching device configured to inactivate the output signal in response to an output of the second delay device,
- wherein each of the first delay device and the second delay device comprise a resistor and a capacitor.
Dependencies are inferred from the claim text.