Delay locked loop circuit and method

A method, comprising:

• providing an external clock signal to a delay locked loop;
• selecting by a selector a first location on a delay line of the delay locked loop;
• accessing a first signal at the first location;
• reducing a phase difference between the first signal and the external clock signal;
• selecting by the selector a second location on the delay line that is different from the first location;
• accessing a second signal at the second location;
• and
• maintaining synchronization between the second signal and the external clock signal to provide an internal clock signal to a synchronous device,
• wherein the selector is configured to receive the first signal and the second signal, and to provide the second signal to a phase detector following a synchronization based upon the first signal.

A method, comprising:

• selecting by a selector a first clock signal from a first portion of a signal delay line;
• synchronizing the first clock signal with a reference clock signal;
• selecting by a selector a second clock signal from a second portion of the signal delay line;
• and
• synchronizing the second clock signal with the reference clock signal,
• wherein the selector is configured to receive the first signal and the second signal, and to provide the second signal to a phase detector following a synchronization based upon the first signal.