Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit

A phase locked loop circuit, comprising:

• a delay compensation circuit adapted to generate a delay clock signal by delaying a phase of a first output clock signal by a second phase, the phase of the first output clock signal having a phase leading a phase of an input clock signal by a first phase, and the second phase corresponding to a delay compensation time greater than a period of the input clock signal and greater than the first phase;
• and
• a phase change circuit adapted to change the second phase to the first phase and to generate a feedback clock signal having a phase synchronized with the phase of the input clock signal in response to the first phase,
• wherein the phase change circuit includes:
• a phase detector adapted to detect a phase difference between the delay clock signal and the feedback clock signal and to generate a difference signal corresponding to the first phase;
• and
• a variable delay circuit adapted to delay the first output clock signal by the first phase in response to the difference signal to generate a feedback clock signal having a phase synchronized with the phase of the input clock signal,
• wherein the first phase is a phase corresponding to a remainder time resulting from the delay compensation time being divided by the period of the input clock, the quotient being an integer.