Apparatus and method for multi-phase clock generation

An apparatus comprising:

• a module configured to receive a clock signal having a first frequency and to generate a first intermediate signal and a second intermediate signal having edges delayed from first edges of the clock signal, each of the first and second intermediate signals having a second frequency that is half of the first frequency, the first and second intermediate signals having a first phase difference of about 180° from each other;
• a first delay element configured to delay the first intermediate signal by a first fixed delay amount to generate a first phase clock signal;
• a second delay element configured to delay the first intermediate signal by a second variable delay amount to generate a second phase clock signal;
• a third delay element configured to delay the second intermediate signal by a third fixed delay amount to generate a third phase clock signal;
• a fourth delay element configured to delay the second intermediate signal by a fourth variable delay amount to generate a fourth phase clock signal;
• and
• a delay detection loop configured to detect a second phase difference between the second phase clock signal and the second intermediate signal or between the fourth phase clock signal and the first intermediate signal, and to adjust the second and fourth variable delay amounts based at least partly on the second phase difference.