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US 8,026,738 B2Granted
Integrated circuit with signal bus formed by cell abutment of logic cells
AssigneeMosaid Technologies Incorporated
InventorsDaniel L. Hillman, William G. Walker
Life of this patent
Estimating the term…
Abstract
An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.
Claims44
An integrated circuit comprising:
- first and second abutting logic cells;
- a signal bus formed at least in part by adjacent portions of each said first and second abutting logic cells and configured to receive a signal for reducing power and distribute the signal to each of said first and second abutting logic cells to place them in a mode of reduced power;
- and
- power reduction circuitry coupled to said first and second abutting logic cells and configured to receive the signal from the signal bus and to control power consumption in said first and second abutting logic cells based on the signal.
1 more element
A method comprising:
- receiving a power reduction signal using a signal bus formed at least in part by adjacent portions of first and second abutting logic cells;
- and
- distributing the power reduction signal to each of the at least two logic cells by way of power reduction circuitry coupled to said first and second abutting logic cells and configured to receive the power reduction signal from the signal bus and to control power consumption in said first and second abutting logic cells based on the power reduction signal.
A standard cell library comprising:
- at least two logic cells;
- a signal bus formed at least in part by adjacent portions of first and second abutting logic cells and configured to receive a power reduction signal and distribute the power reduction signal to each of the at least two logic cells;
- and
- power reduction circuitry coupled to said first and second abutting logic cells and configured to receive the power reduction signal from the signal bus and to control power consumption in said first and second abutting logic cells based on the power reduction signal.
1 more element
An integrated circuit comprising:
- first and second abutting logic cells;
- a polycrystalline silicon layer formed at least in part by adjacent portions of each said first and second abutting logic cells, the polycrystalline silicon layer configured to receive a signal for reducing power and to distribute the signal to each of said first and second logic cells to place them in a mode of reduced power;
- and
- power reduction circuitry coupled to said first and second abutting logic cells and configured to receive the signal from the polycrystalline silicon layer and to control power consumption in said first and second abutting logic cells based on the signal.
1 more element
A method comprising:
- receiving a power reduction signal using a polycrystalline silicon layer formed at least in part by adjacent portions of first and second abutting logic cells;
- and
- distributing the power reduction signal to each of said first and second abutting logic cells by way of power reduction circuitry coupled to said first and second abutting logic cells and configured to receive the power reduction signal from the signal bus and to control power consumption in said first and second abutting logic cells based on the power reduction signal.
Dependencies are inferred from the claim text.