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US 8,026,707 B2Granted
Circuit system and method for reducing an in-rush current
AssigneeMonolithic Power Systems, Inc.
InventorSan Hwa Chee
Life of this patent
Estimating the term…
Abstract
A circuit is provided including an output stage with a pair of transistors. Further provided is a control circuit in communication with the output stage. The control circuit is capable of controlling a duration in which at least one of the transistors is actuated for reducing an in-rush current.
Claims23
A circuit, comprising:
- an output stage including a first transistor and a second transistor, wherein the first transistor is connected to a voltage source, the first transistor and the second transistor are interconnected at an output;
- and
- a control circuit in communication with the output stage, the control circuit capable of controlling a duration during which the second transistor is turned on to shorten the duration gradually for reducing an in-rush current,
- wherein the control circuit is configured to gradually shorten the duration during which the second transistor is turned on thereby reducing the in-rush current,
- wherein the control circuit includes a control circuit comparator,
- wherein the control circuit comparator controls when an oscillator comparator communicates with the output stage,
- wherein the control circuit comparator includes a first input for receiving a ramp down signal, and
- wherein the control circuit comparator includes a second input for receiving a saw tooth signal.
5 more elements
A method, comprising:
- driving an output stage including a first transistor and a second transistor, wherein the first transistor is connected to a voltage source, the first transistor and the second transistor are interconnected at an output;
- and
- using a control circuit for controlling a duration during which the second transistor is turned on for reducing an in-rush current,
- wherein the duration which the second transistor is turned on is gradually shortened thereby reducing the in-rush current,
- wherein current flowing through the output increases when the second transistor is off and decays when the second transistor is on,
- wherein the control circuit includes a control circuit comparator,
- wherein the control circuit comparator controls when an oscillator comparator communicates with the output stage,
- wherein the control circuit comparator includes a first input for receiving a ramp down signal, and
- wherein the control circuit comparator includes a second input for receiving a saw tooth signal.
6 more elements
A circuit, comprising:
- a regulator circuit including a first comparator and an output stage including a first transistor and a second transistor, wherein the first transistor is connected to a voltage source, and the first transistor and the second transistor are interconnected at an output, wherein gates of the first transistor and the second transistor are connected to a common node;
- and
- a control circuit in communication with the regulator circuit and including a second comparator, the control circuit being configured to control a duration during which the first transistor is turned off and the second transistor is turned on to shorten the duration gradually for reducing an in-rush current,
- wherein a voltage applied to the common node selectively turns the first transistor off or on and the second transistor to an opposite state as the first transistor,
- wherein current flowing through the output increases when the second transistor is off and decays when the second transistor is on,
- wherein current flowing through the second transistor causes a change in an output of the first comparator, and
- wherein the second comparator controls when an oscillator comparator communicates with the output stage and includes a first input for receiving a ramp down signal and a second input for receiving a saw tooth signal.
4 more elements
Dependencies are inferred from the claim text.