Voltage regulator for a synchronous clock system to reduce clock tree jitter

A voltage regulator, comprising:

• a first buffer chain configured to delay a clock signal using an external voltage as a supply voltage;
• first and second voltage generating units respectively configured to generate first and second regulated voltages, based on a reference voltage;
• first and second trimming capacitor units configured to control load capacitances respectively of the first and second voltage generating units;
• second and third buffer chains configured to delay the clock signal using respectively the first regulated voltage and the second regulated voltage, as a supply voltage;
• and
• a control unit configured to adjust the load capacitances by comparing clock signals output from the first and second buffer chains and by comparing clock signals output from the first and third buffer chains.