US 8,026,607 B2Granted

Semiconductor apparatus

AssigneeRohm Co., Ltd.

InventorJun Maede

Life of this patent

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Abstract

A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Claims9

Dependent claims

A semiconductor apparatus having a configuration in which a plurality of copper wiring layers and a plurality of insulating layers are alternately layered, and including wiring formed occupying a predetermined region, wherein the wiring includes:

a first wiring pattern formed in a first copper wiring layer, including a plurality of copper wiring members which are formed in parallel with predetermined intervals, and each of which has a rectangular shape extending in a first direction;
and
a second wiring pattern formed in a second copper wiring layer adjacent to the first copper wiring layer, including a plurality of copper wiring members which are formed in parallel with predetermined intervals, and each of which has a rectangular shape extending in a second direction orthogonal to the first direction,
and wherein the region occupied by the first copper wiring pattern, the region occupied by the second copper wiring pattern, and the aforementioned predetermined region at least overlap,
and wherein the first wiring pattern and the second wiring pattern are electrically connected to each other so as to have the same electric potential.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/330,085Filed 8 Dec 2008
Priority: JP JP2007-3163426 Dec 2007
Published: US 2009/0152728 A118 Jun 2009
Granted: 27 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/43
Characterised by their conductive parts: layouts of interconnections
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 20/40
Interconnections in chips, wafers or substrates: interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or…
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs