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US 8,026,579 B2Granted
Silicon pillars for vertical transistors
AssigneeMicron Technology, Inc.
InventorPatrick Thomas
Life of this patent
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Abstract
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.
Claims10
A masking structure for forming semiconductor devices, the masking structure comprising:
- a substrate;
- a first hard mask over the substrate, wherein the first hard mask comprises a plurality of parallel lines;
- and
- a second hard mask directly over a portion of a surface of the first hard mask, wherein the second hard mask is a plurality of islands on the lines of the first hard mask, and wherein another portion of the surface of first hard mask is exposed.
1 more element
Dependencies are inferred from the claim text.