US 8,026,575 B2Granted

Semiconductor device, electronic device, and manufacturing method of the same

AssigneeRenesas Electronics Corporation

InventorHisashi Toyoda

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Abstract

The present invention provides a technology that makes it possible to enhance the gain and the efficiency of an RF bipolar transistor. Device isolation is given between a p+ type isolation region and an n+ type collector embedded region and between a p+ type isolation region and an n type collector region (an n+ type collector extraction region) with an isolation section that surrounds the collector extraction region in a plan view and is formed by embedding a dielectric film in a groove penetrating an isolation section, a collector region, and a collector embedded region and reaching a substrate. Further, a current route is formed between an emitter wiring (a wiring) and the substrate with an electrically conductive layer formed by embedding the electrically conductive layer in a groove penetrating a dielectric film, silicon oxide films, a semiconductor region, and the isolation regions and reaching the substrate, and thereby the impedance between the emitter wiring and the substrate is reduced.

Claims3

Dependent claims

A semiconductor device having a bipolar transistor in a first region over a semiconductor substrate and an emitter pad electrically connected to an emitter of said bipolar transistor in a second region over said semiconductor substrate, said semiconductor device comprising:

a first semiconductor layer formed over said semiconductor substrate and used for a collector of said bipolar transistor;
a second semiconductor layer formed over said first semiconductor layer and used for the collector;
a third semiconductor layer containing silicon germanium, being formed over said second semiconductor layer, and being used for a base of said bipolar transistor;
a fourth semiconductor layer formed in said third semiconductor layer and used for the emitter of said bipolar transistor;
a first electrode formed over said semiconductor substrate, electrically connected to said third semiconductor layer, and used for the base;
a second electrode formed over said semiconductor substrate, electrically connected to said fourth semiconductor layer, and used for the emitter;
a fifth semiconductor layer disposed so as to enclose said third and fourth semiconductor layers in a plan view and electrically connected to said first and second semiconductor layers;
a third electrode formed over said semiconductor substrate, electrically connected to said fifth semiconductor layer, and used for the collector;
a first groove being formed in said second region over said semiconductor substrate and reaching said semiconductor substrate;
a first electrically conductive film being embedded in said first groove and electrically connecting a first pad to said semiconductor substrate;
a second groove disposed so as to enclose said fifth semiconductor layer in a plan view in said first region over said semiconductor substrate and formed so as to penetrate said second and first semiconductor layers and reach said semiconductor substrate;
and
a first dielectric film embedded in said second groove.

10 more elements

An electronic device having a semiconductor chip over a main surface of a supporting substrate, said semiconductor chip having a bipolar transistor in a first region over a semiconductor substrate and an emitter pad electrically connected to an emitter of said bipolar transistor in a second region over said semiconductor substrate,

wherein said semiconductor chip is mounted over said supporting substrate so as to touch a metal frame patterned over said main surface of said supporting substrate, and
wherein said semiconductor chip includes:
a first semiconductor layer formed over said semiconductor substrate and used for a collector of said bipolar transistor;
a second semiconductor layer formed over said first semiconductor layer and used for the collector;
a third semiconductor layer containing silicon germanium, being formed over said second semiconductor layer, and being used for a base of said bipolar transistor;
a fourth semiconductor layer formed in said third semiconductor layer and used for the emitter of said bipolar transistor;
a first electrode formed over said semiconductor substrate, electrically connected to said third semiconductor layer, and used for the base;
a second electrode formed over said semiconductor substrate, electrically connected to said fourth semiconductor layer, and used for the emitter;
a fifth semiconductor layer disposed so as to enclose said third and fourth semiconductor layers in a plan view and electrically connected to said first and second semiconductor layers;
a third electrode formed over said semiconductor substrate, electrically connected to said fifth semiconductor layer, and used for the collector;
a first groove being formed in said second region over said semiconductor substrate and reaching said semiconductor substrate;
a first electrically conductive film being embedded in said first groove and electrically connecting a first pad to said semiconductor substrate;
a second groove disposed so as to enclose said fifth semiconductor layer in a plan view in said first region over said semiconductor substrate and formed so as to penetrate said second and first semiconductor layers and reach said semiconductor substrate;
and
a first dielectric film embedded in said second groove.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/435,771Filed 5 May 2009 · division
Priority: JP 2006-0327589 Feb 2006
Published: US 2009/0218658 A13 Sep 2009
Granted: 27 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 10/891
Vertical heterojunction BJTs: comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors
H10D 10/021
Manufacture or treatment: of heterojunction BJTs [HBT]
H10D 64/231
Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes: emitter or collector…
H10W 70/479
Leadframes: on or in insulating or insulated package substrates, interposers, or redistribution layers

Family

Application11/703,256Parent of this division · filed 7 Feb 2007
US 2009/0218658 A1Pre-grant publication · published 3 Sep 2009
US 7,547,958 B2Parent of this division
US 2007/0181976 A1Published application
US 8,026,575 B2This patent

From the US filing history. Foreign family members aren’t listed.