Anti-fuse memory cell
AssigneeSidense Corp.
InventorsWlodek Kurjanowicz, Steven Smith
Life of this patent
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Abstract
An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.
Claims5
A non-volatile memory cell formed on a substrate with a CMOS fabrication process capable of forming structures with a predefined minimum feature size i, where i is a numerical value in nm, comprising:
- a polysilicon gate over a channel region having a channel length and a channel width;
- a diffusion region proximate to a first end of the channel region;
- a field oxide region proximate to a second end of the channel region;
- a variable thickness gate oxide between the polysilicon gate and the substrate, the variable thickness gate oxide having a thick gate oxide portion and a thin gate oxide portion fusible to form a conductive link between the polysilicon gate and the substrate, the thin gate oxide portion being formed over the channel region and having dimensions less than the minimum feature size i.
Dependencies are inferred from the claim text.