US 8,026,553 B2Granted

Semiconductor memory device and manufacturing method thereof

AssigneeKabushiki Kaisha Toshiba

InventorTomoaki Shino

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Abstract

This disclosure concerns a memory comprising a semiconductor layer extending in a first direction; a source; a drain; a body between the source and the drain; a bit-line extending in the first direction; a first gate-dielectric on a first side-surface of the body; a first gate-electrode on the first side-surface of the body via the first gate dielectric film; a first gate line extending in the first direction, connected to a bottom of the first gate-electrode, and formed integratedly with the first gate-electrode using same material; a second gate dielectric on a second side-surface of the body; a second gate-electrode on the second side surface of the body via the second gate dielectric film; and a second gate line extending in a second direction crossing the first direction, connected to an upper portion of the second gate-electrode, and formed integratedly with the second gate-electrode using same material.

Claims12

Dependent claims

A semiconductor memory device comprising:

a supporting substrate;
a semiconductor layer provided above the supporting substrate, and extending in a first direction;
a source layer provided in the semiconductor layer;
a drain layer provided in the semiconductor layer;
a body provided between the source layer and the drain layer in the semiconductor layer, the body being in an electrically floating state, electric charges being accumulated in or emitted from the body to store data;
a bit line connected to the drain layer, and extending in the first direction;
a first gate dielectric film provided on a first side surface of the body;
a first gate electrode provided on the first side surface of the body via the first gate dielectric film;
a first gate line extending in the first direction, connected to a bottom of the first gate electrode, and formed integrally with the first gate electrode using same material;
a second gate dielectric film provided on a second side surface of the body, the second side surface being opposite to the first side surface;
a second gate electrode provided on the second side surface of the body via the second gate dielectric film, the second gate electrode extending upward above a top surface of the body and isolated from the first gate electrode;
and
a second gate line extending above the body in a second direction crossing the first direction, connected to an upper portion of the second gate electrode, and formed integrally with the second gate electrode using same material.

10 more elements

A semiconductor memory device comprising:

a supporting substrate;
a semiconductor layer provided above the supporting substrate, and extending in a first direction;
a source layer provided in the semiconductor layer;
a drain layer provided in the semiconductor layer;
a body provided between the source layer and the drain layer in the semiconductor layer, the body being in an electrically floating state, electric charges being accumulated in or emitted from the body to store data;
a bit line connected to the drain layer, and extending in the first direction;
a first gate dielectric film provided on a first side surface of the body;
a first gate electrode provided on the first side surface of the body via the first gate dielectric film and connected to the supporting substrate;
a second gate dielectric film provided on a second side surface of the body, the second side surface being opposite to the first side surface;
a second gate electrode provided on the second side surface of the body via the second gate dielectric film, the second gate electrode extending upward above a top surface of the body and isolated from the first gate electrode;
and
a second gate line extending above the body in a second direction crossing the first direction, connected to an upper portion of the second gate electrode, and formed integrally with the second gate electrode using same material.

9 more elements

A semiconductor memory device comprising:

a supporting substrate;
a semiconductor layer provided above the supporting substrate, and extending in a first direction;
a source layer provided in the semiconductor layer;
a drain layer provided in the semiconductor layer;
a body provided between the source layer and the drain layer in the semiconductor layer, the body being in an electrically floating state, electric charges being accumulated in or emitted from the body to store data;
a bit line connected to the drain layer, and extending in the first direction;
a first gate dielectric film provided on a first side surface of the body;
a first gate electrode provided on the first side surface of the body via the first gate dielectric film and including a first part and a second part;
a second gate dielectric film provided on a second side surface of the body, the second side surface being opposite to the first side surface;
a second gate electrode provided on the second side surface of the body via the second gate dielectric film, the second gate electrode extending upward above a top surface of the body and isolated from the first gate electrode;
and
a second gate line extending above the body in a second direction crossing the first direction, connected to an upper portion of the second gate electrode, and formed integrally with the second gate electrode using same material, wherein
a first part is provided below the second gate line and includes two side surfaces facing to the first direction, and
a second part includes a top surface located lower than a top surface of the first part.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/114,205Filed 2 May 2008
Priority: JP 2007-12596810 May 2007
Published: US 2008/0277725 A113 Nov 2008
Granted: 27 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 86/201
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
H10B 12/00
Dynamic random access memory [dram] devices
H10B 12/01
Dynamic random access memory [DRAM] devices: manufacture or treatment
H10B 12/20
Dynamic random access memory [DRAM] devices: dRAM devices comprising floating-body transistors, e.g. floating-body cells